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ds07-13744-2e fujitsu semiconductor data sheet copyright?2006-2007 fujitsu limited all rights reserved ?check sheet? is seen at the following support page url : http://www.fujitsu.com/global/services/micr oelectronics/product/micom/support/index.html ?check sheet? lists the minimal require ment items to be checked to prevent problems beforehand in system development. be sure to refer to the ?check sheet? for the latest cautions on development. 16-bit proprietary microcontrollers cmos f 2 mc-16lx mb90350e series mb90f351e (s) , mb90f351te (s) , mb90f352e (s) , mb90f352te (s) , mb90351e (s) , mb90351te (s) , mb90352e (s) , mb90352te (s) , mb90f356e (s) , mb90f356te (s) , mb90f357e (s) , mb90f357te (s) , mb90356e (s) , mb90356te (s) , mb90357e (s) , mb90357te(s) , mb90v340e-101/102/103/104 description the mb90350e series, loaded 1 channel full-can* inte rface and flash rom, is general-purpose fujitsu 16-bit microcontroller designing for automotive and indu strial applications. its main feature is the on-board can interface, which conforms to can stand ard version2.0 part a and part b, wh ile supporting a very flexible message buffer scheme and so offering more functions than a normal full can appro ach. with the new 0.35 m cmos technology, fujitsu now offers on-chip flash rom program memory up to 128 kbytes. the power supply (3 v) is supplied to the mcu core from an internal regulator circuit. this creates a major advantage in terms of emi and power consumption. the pll clock multiplication circuit provides an internal 42 ns instruction execution time from an external 4 mhz clock. also, the clock supervisor function c an monitor main clock and sub clock independently. as the peripheral resources, the unit features a 4-cha nnel output compare unit, 6- channel input capture unit, 2 separate 16-bit free-run timers, 2-channel uart and 15-channel 8/10-bit a/d converter built-in. * : controller area network (can) - license of robert bosch gmbh note : f 2 mc is the abbreviation of fuji tsu flexible microcontroller.
mb90350e series 2 features ? clock ? built-in pll clock frequency multiplication circuit selection of machine clocks (pll clocks) is allowed among frequency division by two on oscillation clock, and multiplication of 1 to 6 times of oscillation cloc k (for 4 mhz oscillation clock, 4 mhz to 24 mhz). operation by sub clock (up to 50 khz : 100 khz oscillation clock divided by two) is allowed (devices without s-suffix only) . minimum execution time of instruction : 42 ns (when operating with 4-mhz oscillation clock, and 6-time multiplied pll clock). built-in clock modulation circuit ? 16 mbytes cpu memory space 24-bit internal addressing ? instruction system best suited to controller wide choice of data types (bit, byte, word, and long word) wide choice of addres sing modes (23 types) enhanced multiply-divide instructions with sign and reti instructions ? clock supervisor (mb90x356x and mb90x357x only) main clock or sub clock is monitored independently. internal cr oscillation clock (100 khz typical) can be used as sub clock. ? enhanced high-precision computing with 32-bit accumulator ? instruction system compatible with high- level language (c language) and multitask employing system stack pointer enhanced various pointer indirect instructions barrel shift instructions ? increased processing speed 4-byte instruction queue ? powerful interrupt function powerful 8-level, 34-condition interrupt feature up to 8 channels external interrupts are supported. ? automatic data transfer fu nction independent of cpu extended intelligent i/o service function (ei 2 os) : up to 16 channels dma : up to 16 channels ? low power consumption (standby) mode sleep mode (a mode that stops cpu operating clock) main timer mode (a timebase timer mo de switched from the main clock mode) pll timer mode (a timebase timer mode switched from the pll clock mode) watch mode (a mode that operates sub clock and watch timer only) stop mode (a mode that stops oscillation clock and sub clock) cpu intermittent operation mode ? process cmos technology ? i/o port general-purpose input/output port (cmos output) - 49 ports (devices without s-suffix : devices that correspond to sub clock) - 51 ports (devices with s-suffix : devi ces that do not correspond to sub clock) (continued)
mb90350e series 3 ? sub clock pin (x0a, x1a) yes (using the external oscilla tion) : devices without s-suffix no (using the sub clock mode at internal cr oscillation) : devices with s-suffix ? timer timebase timer, watch timer, watchdog timer : 1 channel 8/16-bit ppg timer : 8-bit 10 channels or 16-bit 6 channels 16-bit reload timer : 2 channels (only evaluation products has 4 channels) 16- bit input/output timer - 16-bit free-run timer : 2 channels (frt0 : icu0/1, frt1 : icu4/5/6/7, ocu4/5/6/7) - 16- bit input capture: (icu) : 6 channels - 16-bit output compare : (ocu) : 4 channels ? full-can interface : 1 channel compliant with can standard version2.0 part a and part b 16 message buffers are built-in can wake-up function ? uart (lin/sci) : 2 channels equipped with full-duplex double buffer clock-asynchronous or clock-synchronous serial transmission is available. ? i 2 c interface* 1 : 1 channel up to 400 kbps transfer rate ? dtp/external interrupt : 8 channels, can wakeup : 1 channel module for activation of extended intelligent i/o service (ei 2 os), dma, and generation of external interrupt by external input. ? delay interrupt generator module generates interrupt request for task switching. ? 8/10-bit a/d converter : 15 channels resolution is selectable between 8-bit and 10-bit. activation by external trigger input is allowed. conversion time : 3 s (at 24-mhz machine clock, including sampling time) ? program patch function address matching detection for 6 address pointers. ? capable of changing input voltage level for port automotive/cmos-schmitt (initial level is automotive in single chip mode) ttl level (corresponds to external bus pins only, init ial level of these pins is ttl in external bus mode) ? low voltage/cpu operation detection reset (devices with t-suffix) detects low voltage (4.0 v 0.3 v) and resets automatically resets automatically when program is runaway and counter is not cleared within interval time (approx. 262 ms : external 4 mhz) ? dual operation flash memory erase/write and read can be executed in the differ ent bank (upper bank/lower bank) at the same time. ? supported t a = + 125 c the maximum operating frequency is 24 mhz* 2 : (at t a = + 125 c) . (continued)
mb90350e series 4 (continued) ? flash security function ? protects the content of flash memory (mb90f352x, mb90f357x only) ? external bus interface 4 mbytes external memory space mb90f351e(s), mb90f351te(s), mb90f352e(s), mb90f352t e(s) : external bus interface can not be used in internal vector mode. it can be used only in external vector mode. *1 : i 2 c license : purchase of fujitsu i 2 c components conveys a license under the philips i 2 c patent rights to use, these components in an i 2 c system provided that the system conforms to the i 2 c standard specification as defined by philips. *2 : if used exceeding t a = + 105 c, be sure to contact fujitsu for reliability limitations.
mb90350e series 5 product lineup1 (without clock supervisor function) flash memory products (continued) part number parameter mb90f351e, mb90f352e mb90f351te, mb90f352te mb90f351es, mb90f352es mb90f351tes, mb90f352tes type flash memory products cpu f 2 mc-16lx cpu system clock pll clock multiplication circuit ( 1, 2, 3, 4, 6, 1/2 when pll stops) minimum instruction execution time : 42 ns (oscillation clock 4 mhz, pll 6) rom 64 kbytes flash memory : mb90f351e(s), mb90f351te(s) 128 kbytes dual operation flash memory (e rase/write and read can be operated at the same time) : mb90f352e(s), mb90f352te(s) ram 4 kbytes emulator-specific power supply* 1 ? sub clock pin (x0a, x1a) (max 100 khz) yes no clock supervisor no low voltage/cpu operation detection reset no yes no yes operating voltage 3.5 v to 5.5 v : at normal opera ting (not using a/d converter) 4.0 v to 5.5 v : at using a/ d converter/flash programming 4.5 v to 5.5 v : at using external bus operating temperature ? 40 c to + 125 c package lqfp-64 uart 2 channels wide range of baud rate settings using a dedicated reload timer special synchronous options for adapting to different synchronous serial protocols lin functionality working either as master or slave lin device i 2 c (400 kbps) 1 channel a/d converter 15 channels 10-bit or 8-bit resolution conversion time : min 3 s includes sample time (per one channel) 16-bit reload timer (2 channels) operation clock frequency : fsys/2 1 , fsys/2 3 , fsys/2 5 (fsys = machine clock frequency) supports external event count function. 16-bit i/o timer (2 channels) i/o timer 0 (clock input frck0) corresponds to icu0/1. i/o timer 1 (clock input frck1) corresponds to icu4/5/6/7, ocu4/5/6/7. signals an interrupt when overflowing. supports timer clear when it matche s output compare (ch.0, ch.4) . operation clock frequency : fsys, fsys/2 1 , fsys/2 2 , fsys/2 3 , fsys/2 4 , fsys/2 5 , fsys/2 6 , fsys/2 7 (fsys = machine clock frequency) 16-bit output compare 4 channels signals an interrupt when 16-bit i/o time r matches with output compare registers. a pair of compare registers can be used to generate an output signal.
mb90350e series 6 (continued) *1 : it is setting of jumper switch (t ool vcc) when emulator (mb2147-01) is used. please refer to the emulator hardware manual about details. *2 : embedded algorithm is a trademark of advanced micro devices inc. part number parameter mb90f351e, mb90f352e mb90f351te, mb90f352te mb90f351es, mb90f352es mb90f351tes, mb90f352tes 16-bit input capture 6 channels retains free-run timer value by (rising edge, falling edge or rising & falling edge) , signals an interrupt. 8/16-bit programmable pulse generator 6 channels (16-bit)/10 channels (8-bit) 8-bit reload counters 12 8-bit reload registers for l pulse width 12 8-bit reload registers for h pulse width 12 supports 8-bit and 16-bit operation modes. a pair of 8-bit reload counters can be conf igured as one 16-bit reload counter or as 8-bit prescaler + 8-bit reload counter. operation clock frequency : fsys, fsys/2 1 , fsys/2 2 , fsys/2 3 , fsys/2 4 or 128 s@fosc = 4 mhz (fsys = machine clock frequency, fosc = oscillation clock frequency) can interface 1 channel compliant with can standard version2.0 part a and part b. automatic re-transmission in case of error automatic transmission responding to remote frame 16 prioritized message buf fers for data and id supports multiple messages. flexible configuration of acceptance filtering : full bit compare/full bit mask/two partial bit masks supports up to 1 mbps. external interrupt 8 channels can be used rising edge, falling edge, starting up by ?h?/?l? level input, external interrupt, extended intelligent i/o services (ei 2 os) and dma. d/a converter ? i/o ports virtually all external pins can be used as general purpose i/o port. all push-pull outputs bit-wise settable as input/output or peripheral signal settable as cmos schmitt trigger/ automotive inputs ttl input level settable for exter nal bus (only for external bus pin) flash memory supports automatic programming, embedded algorithm tm * 2 write/erase/erase-suspend/resume commands a flag indicating completion of the algorithm number of erase cycles : 10000 times data retention time : 20 years boot block configuration erase can be performed on each block. block protection with external programming voltage flash security feature for protecting th e content of the flash (mb90f352e(s) and mb90f352te(s) only) corresponding evaluation name mb90v340e-102 mb90v340e-101
mb90350e series 7 mask rom products/evaluation products (continued) part number parameter mb90351e, mb90352e mb90351te, mb90352te mb90351es, mb90352es mb90351tes, mb90352tes mb90v340e- 101 mb90v340e- 102 type mask rom products evaluation products cpu f 2 mc-16lx cpu system clock pll clock multiplication circuit ( 1, 2, 3, 4, 6, 1/2 when pll stops) minimum instruction execution time : 42 ns (oscillation clock 4 mhz, pll 6) rom mask rom 64 kbytes : mb90351e(s), mb90351te(s) 128 kbytes : mb90352e(s), mb90352te(s) external ram 4 kbytes 30 kbytes emulator-specific power supply* ? yes sub clock pin (x0a, x1a) (max 100 khz) yes no no yes clock supervisor no low voltage/cpu operation detection reset no yes no yes no operating voltage range 3.5 v to 5.5 v : at normal operating (not using a/d converter) 4.0 v to 5.5 v : at using a/d converter 4.5 v to 5.5 v : at using external bus 5 v 10 % operating temperature range ? 40 c to + 125 c ? package lqfp-64 pga-299 uart 2 channels 5 channels wide range of baud rate settings using a dedicated reload timer special synchronous options for adapting to different synchronous serial protocols lin functionality working either as master or slave lin device i 2 c (400 kbps) 1 channel 2 channels a/d converter 15 channels 24 channels 10-bit or 8-bit resolution conversion time : min 3 s includes sample time (per one channel) 16-bit reload timer 2 channels 4 channels operation clock frequency : fsys/2 1 , fsys/2 3 , fsys/2 5 (fsys = machine clock frequency) supports external event count function. 16-bit i/o timer (2 channels) i/o timer 0 (clock input frck0) corresponds to icu0/1. i/o timer 1 (clock input frck1) corresponds to icu4/5/6/7, ocu4/5/6/7. i/o timer 0 corresponds to icu0/1/2/3, ocu0/1/2/3. i/o timer 1 corresponds to icu4/5/6/7, ocu4/5/6/7. signals an interrupt when overflowing. supports timer clear when it matche s output compare (ch.0, ch.4) . operation clock frequency : fsys, fsys/2 1 , fsys/2 2 , fsys/2 3 , fsys/2 4 , fsys/2 5 , fsys/2 6 , fsys/2 7 (fsys = machine clock frequency)
mb90350e series 8 (continued) * : it is setting of jumper switch (tool vcc) when emulator (mb2147-01) is used. please refer to the emulator hardware manual about details. part number parameter mb90351e, mb90352e mb90351te, mb90352te mb90351es, mb90352es mb90351tes, mb90352tes mb90v340e- 101 mb90v340e- 102 16-bit output compare 4 channels 8 channels signals an interrupt when 16-bit i/o ti mer matches output compare registers. a pair of compare registers can be used to generate an output signal. 16-bit input capture 6 channels 8 channels retains free-run timer value by (rising edge, fa lling edge, or the both edges), signals an interrupt. 8/16-bit programmable pulse generator 6 channels (16-bit)/10 channels (8-bit) 8-bit reload counters 12 8-bit reload registers for l pulse width 12 8-bit reload registers for h pulse width 12 8 channels (16-bit)/ 16 channels (8-bit) 8-bit reload counters 16 8-bit reload registers for l pulse width 16 8-bit reload registers for h pulse width 16 supports 8-bit and 16-bit operation modes. a pair of 8-bit reload counters can be conf igured as one 16-bit reload counter or as 8-bit prescaler + 8-bit reload counter. operation clock frequency : fsys, fsys/2 1 , fsys/2 2 , fsys/2 3 , fsys/2 4 or 128 s@fosc = 4 mhz (fsys = machine clock frequency, fosc = oscillation clock frequency) can interface 1 channel 3 channels compliant with can standard ve rsion 2.0 part a and part b. automatic re-transmission in case of error automatic transmission responding to remote frame 16 prioritized message buf fers for data and id supports multiple messages. flexible configuration of acceptance filtering : full bit compare/full bit mask/two partial bit masks supports up to 1 mbps. external interrupt 8 channels 16 channels can be used rising edge, falling edge, starting up by ?h?/?l? level input, external interrupt, extended intelligent i/o services (ei 2 os) and dma. d/a converter ? 2 channels i/o ports virtually all external pins can be used as general purpose i/o port. all push-pull outputs bit-wise settable as input/output or peripheral signal settable as cmos schmitt trigger/ automotive inputs ttl input level settable for exter nal bus (only for external bus pin) flash memory ? corresponding evaluation name mb90v340e-102 mb90v340e-101 ?
mb90350e series 9 product lineup 2 (with clock supervisor function) flash memory products (continued) part number parameter mb90f356e, mb90f357e mb90f356te, mb90f357te mb90f356es, mb90f357es mb90f356tes, mb90f357tes type flash memory products cpu f 2 mc-16lx cpu system clock on-chip pll clock multiplier ( 1, 2, 3, 4, 6, 1/2 when pll stops) minimum instruction execution time : 42 ns (oscillation clock 4 mhz, pll 6) rom dual operation flash memory 64 kbytes : mb90f356e(s), mb90f356te(s) 128 kbytes : mb90f357e(s), mb90f357te(s) ram 4 kbytes emulator-specific power supply* 1 ? sub clock pin (x0a, x1a) yes no (internal cr oscillation can be used as sub clock) clock supervisor yes low voltage/cpu operation detection reset no yes no yes operating voltage range 3.5 v to 5.5 v : at normal opera ting (not using a/d converter) 3.5 v to 5.5 v : at using a/ d converter/flash programming 3.5 v to 5.5 v : at using external bus operating temperature range ? 40 c to + 125 c package lqfp-64 uart 2 channels wide range of baud rate settings using a dedicated reload timer special synchronous options for adapting to different synchronous serial protocols lin functionality working either as master or slave lin device i 2 c (400 kbps) 1 channel a/d converter 15 channels 10-bit or 8-bit resolution conversion time : min 3 s includes sample time (per one channel) 16-bit reload timer (4 channels) operation clock frequency : fsys/2 1 , fsys/2 3 , fsys/2 5 (fsys = machine clock frequency) supports external event count function. 16-bit i/o timer (2 channels) i/o timer 0 (clock input frck0) corresponds to icu 0/1. i/o timer 1 (clock input frck1) corr esponds to icu 4/5/6/7, ocu 4/5/6/7. signals an interrupt when overflowing. supports timer clear when a match with output compare (channel 0, 4) . operation clock frequency : fsys, fsys/2 1 , fsys/2 2 , fsys/2 3 , fsys/2 4 , fsys/2 5 , fsys/2 6 , fsys/2 7 (fsys = machine clock frequency) 16-bit output compare 4 channels signals an interrupt when 16-bit i/o time r matches with output compare registers. a pair of compare registers can be used to generate an output signal.
mb90350e series 10 (continued) *1 : it is setting of jumper switch (t ool vcc) when emulator (mb2147-01) is used. please refer to the emulator hardware manual about details. *2 : embedded algorithm is a trademark of advanced micro devices inc. part number parameter mb90f356e, mb90f357e mb90f356te, mb90f357te mb90f356es, mb90f357es mb90f356tes, mb90f357tes 16-bit input capture 6 channels retains free-run timer value by (rising edge, fa lling edge or rising & falling edge), signals an interrupt. 8/16-bit programmable pulse generator 6 channels (16-bit)/10 channels (8-bit) 8-bit reload counters 12 8-bit reload registers for l pulse width 12 8-bit reload registers for h pulse width 12 supports 8-bit and 16-bit operation modes. a pair of 8-bit reload counters can be conf igured as one 16-bit reload counter or as 8-bit prescaler + 8-bit reload counter. operation clock frequency : fsys, fsys/2 1 , fsys/2 2 , fsys/2 3 , fsys/2 4 or 128 s@fosc = 4 mhz (fsys = machine clock frequency, fosc = oscillation clock frequency) can interface 1 channel conforms to can specificati on version 2.0 part a and b. automatic re-transmission in case of error automatic transmission responding to remote frame prioritized 16 message buffers for data and id supports multiple messages. flexible configuration of acceptance filtering : full bit compare/full bit mask/two partial bit masks supports up to 1 mbps. external interrupt 8 channels can be used rising edge, falling edge, starting up by h/l level input, external interrupt, extended intelligent i/o services (ei 2 os) and dma. d/a converter ? i/o ports virtually all external pins can be used as general purpose i/o port. all push-pull outputs bit-wise settable as input/output or peripheral module signal settable as cmos schmitt trigger/ automotive inputs ttl input level settable for exter nal bus (only for external bus pin) flash memory supports automatic programming, embedded algorithm tm * 2 write/erase/erase-suspend/resume commands a flag indicating completion of the algorithm number of erase cycles : 10000 times data retention time : 10 years boot block configuration erase can be performed on each block. block protection with external programming voltage flash security feature for protecting th e content of the flash (mb90f357x only) corresponding eva name mb90v340e-104 mb90v340e-103
mb90350e series 11 mask rom products/evaluation products (continued) part number parameter mb90356e, mb90357e mb90356te, mb90357te mb90356es, mb90357es mb90356tes, mb90357tes mb90v340e- 103 mb90v340e- 104 cpu f 2 mc-16lx cpu system clock on-chip pll clock multiplier ( 1, 2, 3, 4, 6, 1/2 when pll stops) minimum instruction execution time : 42 ns (oscillation clock 4 mhz, pll 6) rom mask rom 64 kbytes :mb90356e(s), mb90356te(s) 128 kbytes :mb90357e(s), mb90357te(s) external ram 4 kbytes 30 kbytes emulator-specific power supply* ? yes sub clock pin (x0a, x1a) yes no (internal cr oscillation can be used as sub clock) no (internal cr oscillation can be used as sub clock) yes clock supervisor yes low voltage/cpu operation detection reset no yes no yes no operating voltage range 3.5 v to 5.5 v : at normal operating (not using a/d converter) 4.0 v to 5.5 v : at using a/d converter 4.5 v to 5.5 v : at using external bus 5 v 10% operating temperature range ? 40 c to + 125 c ? package lqfp-64 pga-299 uart 2 channels 5 channels wide range of baud rate settings using a dedicated reload timer special synchronous options for adapting to different synchronous serial protocols lin functionality working either as master or slave lin device i 2 c (400 kbps) 1 channel 2 channels a/d converter 15 channels 24 channels 10-bit or 8-bit resolution conversion time : min 3 s includes sample time (per one channel) 16-bit reload timer (4 channels) operation clock frequency : fsys/2 1 , fsys/2 3 , fsys/2 5 (fsys = machine clock frequency) supports external event count function. 16-bit i/o timer (2 channels) i/o timer 0 (clock input frck0) corresponds to icu 0/1. i/o timer 1 (clock input frck1) corresponds to icu 4/5/6/7, ocu 4/5/6/7. i/o timer 0 corresponds to icu 0/1/2/3, ocu 0/1/2/3. i/o timer 1 corresponds to icu 4/5/6/7, ocu 4/5/6/7. signals an interrupt when overflowing. supports timer clear when a match with output compare (channel 0, 4) . operation clock frequency : fsys, fsys/2 1 , fsys/2 2 , fsys/2 3 , fsys/2 4 , fsys/2 5 , fsys/2 6 , fsys/2 7 (fsys = machine clock frequency)
mb90350e series 12 (continued) * : it is setting of jumper switch (tool vcc) when emulator (mb2147-01) is used. please refer to the emulator hardware manual about details. part number parameter mb90356e, mb90357e mb90356te, mb90357te mb90356es, mb90357es mb90356tes, mb90357tes mb90v340e- 103 mb90v340e- 104 16-bit output compare 4 channels 8 channels signals an interrupt when 16-bit i/o time r matches with output compare registers. a pair of compare registers can be used to generate an output signal. 16-bit input capture 6 channels 8 channels retains free-run timer value by (rising edge, fa lling edge or rising & falling edge), signals an interrupt. 8/16-bit programmable pulse generator 6 channels (16-bit)/10 channels (8-bit) 8-bit reload counters 12 8-bit reload registers for l pulse width 12 8-bit reload registers for h pulse width 12 8 channels (16-bit)/ 16 channels (8-bit) 8-bit reload counters 16 8-bit reload registers for l pulse width 16 8-bit reload registers for h pulse width 16 supports 8-bit and 16-bit operation modes. a pair of 8-bit reload counters can be conf igured as one 16-bit reload counter or as 8-bit prescaler + 8-bit reload counter. operation clock frequency : fsys, fsys/2 1 , fsys/2 2 , fsys/2 3 , fsys/2 4 or 128 s@fosc = 4 mhz (fsys = machine clock frequency, fosc = oscillation clock frequency) can interface 1 channel 3 channels conforms to can specificati on version 2.0 part a and b. automatic re-transmission in case of error automatic transmission responding to remote frame prioritized 16 message buffers for data and id supports multiple messages. flexible configuration of acceptance filtering : full bit compare/full bit mask/two partial bit masks supports up to 1 mbps. external interrupt 8 channels 16 channels can be used rising edge, falling edge, starting up by h/l level input, external interrupt, extended intelligent i/o services (ei 2 os) and dma. d/a converter ? 2 channels i/o ports virtually all external pins can be used as general purpose i/o port. all push-pull outputs bit-wise settable as input/output or peripheral module signal settable as cmos schmitt trigger/ automotive inputs ttl input level settable for exter nal bus (only for external bus pin) flash memory ? corresponding eva name mb90v340e-104 mb90v340e-103 ?
mb90350e series 13 packages and product correspondence : yes, : no note : refer to ? package dimensions? for detail of each package. package mb90v340e-101, mb90v340e-102, mb90v340e-103, mb90v340e-104 mb90f351e (s) , mb90f351te (s) mb90f352e (s) , mb90f352te (s) mb90f356e (s) , mb90f356te (s) mb90f357e (s) , mb90f357te (s) mb90351e (s) , mb90351te (s) mb90352e (s) , mb90352te (s) mb90356e (s) , mb90356te (s) mb90357e (s) , mb90357te (s) pga-299c-a01 fpt-64p-m23 (12.0 mm , 0.65 mm pitch) fpt-64p-m24 (10.0 mm , 0.50 mm pitch)
mb90350e series 14 pin assignments mb90f351e(s), mb90f351te(s), mb90f352e(s), mb90f352te(s),mb90f356e(s), mb90f356te(s), mb90f357e(s), mb90f357te(s), mb90351e(s), mb90351te(s), mb90352e(s), mb90352te(s), mb90356e(s), mb90356te(s), mb90357e(s), mb90357te(s) (top view) (fpt-64p-m23, fpt-64p-m24) * : devices without s-suffix : x0a, x1a devices with s-suffix : p40, p41 4 8 47 46 45 44 4 3 42 41 40 3 9 38 3 7 3 6 3 5 3 4 33 64 6 3 62 61 60 59 5 8 57 56 55 54 5 3 52 51 50 49 17 1 8 19 20 21 22 2 3 24 25 26 27 2 8 29 3 0 3 1 3 2 avcc p61/an1 p60/an0 p 3 7/clk/out7 p 3 6/rdy/out6 p 3 5/hak /out5 p 3 4/hrq/out4 p 3 2/wrl /wr/int10r p 3 1/rd/in5 p 3 0/ale/in4 p45/ s cl0/frck1 p44/ s da0/frck0 p25/a21/in1/adtg c vcc p 33 /wrh 10 11 12 1 3 14 15 16 12 3 4567 9 8 p10/ad0 8 /tin1 p07/ad07/int15 p06/ad06/int14 p05/ad05/int1 3 p04/ad04/int12 p0 3 /ad0 3 /int11 p02/ad02/int10 p01/ad01/int9 p00/ad00/int 8 md0 md1 md2 p41/x1a * p40/x0a * v ss p4 3 /in7/tx1 v ss x0 x1 r s t p24/a20/in0 p2 3 /a19/ppgf(e) p22/a1 8 /ppgd(c) p21/a17/ppgb(a) p20/a16/ppg9( 8 ) p17/ad15 p16/ad14 p15/ad1 3 p14/ad12/ s ck 3 p1 3 /ad11/ s ot 3 p12/ad10/ s in 3 /int11r p11/ad09/tot1 av ss avrh p64/an4/ppg 8 (9) p65/an5/ppga(b) p66/an6/ppgc(d) p67/an7/ppge(f) p50/an 8 / s in2 p51/an9/ s ot2 p52/an10/ s ck2 p5 3 /an11/tin 3 p56/an14 p55/an1 3 p54/an12/tot 3 p62/an2/ppg4(5) p6 3 /an 3 /ppg6(7) p42/in6/rx1/int9r
mb90350e series 15 pin description (continued) pin no. pin name i/o circuit type* function 46 x1 a oscillation output pin 47 x0 oscillation input pin 45 rst e reset input pin 3 to 8 p62 to p67 i general purpose i/o ports an2 to an7 analog input pins for a/d converter ppg4 (5) , 6 (7) , 8 (9) , a (b) , c (d) , e (f) output pins for ppgs 9 p50 o general purpose i/o port an8 analog input pin for a/d converter sin2 serial data input pin for uart2 10 p51 i general purpose i/o port an9 analog input pin for a/d converter sot2 serial data output pin for uart2 11 p52 i general purpose i/o port an10 analog input pin for a/d converter sck2 serial clock i/o pin for uart2 12 p53 i general purpose i/o port an11 analog input pin for a/d converter tin3 event input pin for reload timer3 13 p54 i general purpose i/o port an12 analog input pin for a/d converter tot3 output pin for reload timer3 14, 15 p55, p56 i general purpose i/o ports an13, an14 analog input pins for a/d converter 16 p42 f general purpose i/o port in6 data sample input pin for input capture icu6 rx1 rx input pin for can1 int9r external interrupt request input pin for int9 17 p43 f general purpose i/o port in7 data sample input pin for input capture icu7 tx1 tx output pin for can1 19, 20 p40, p41 f general purpose i/o ports (devices with s-suffix and mb90v340e-101/103) x0a, x1a b x0a : oscillation input pins for sub clock x1a : oscillation output pins for sub clock (devices without s-suffix and mb90v340e-102/104)
mb90350e series 16 (continued) pin no. pin name i/o circuit type* function 24 to 31 p00 to p07 g general purpose i/o ports. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad00 to ad07 input/output pins of external address da ta bus lower 8 bits. this function is enabled when the exte rnal bus is enabled. int8 to int15 external interrupt r equest input pins for int8 to int15 32 p10 g general purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad08 input/output pin for external bus address data bus bit 8. this function is enabled wh en external bus is enabled. tin1 event input pin for reload timer1 33 p11 g general purpose i/o port. the register c an be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad09 input/output pin for external bus addre ss data bus bit 9. this function is enabled when external bus is enabled. tot1 output pin for reload timer1 34 p12 n general purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad10 input/output pin for external bus addre ss data bus bit 10. this function is enabled when external bus is enabled. sin3 serial data input pin for uart3 int11r external interrupt request input pin for int11 35 p13 g general purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad11 input/output pin for external bus address data bus bit 11. this function is enabled wh en external bus is enabled. sot3 serial data output pin for uart3 36 p14 g general purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad12 input/output pin for external bus address data bus bit 12. this function is enabled wh en external bus is enabled. sck3 clock input/output pin for uart3 37 p15 n general purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad13 input/output pin for external bus address data bus bit 13. this function is enabled wh en external bus is enabled. 38 p16 g general purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad14 input/output pin for external bus address data bus bit 14. this function is enabled wh en external bus is enabled.
mb90350e series 17 (continued) pin no. pin name i/o circuit type* function 39 p17 g general purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad15 input/output pin for external bus address data bus bit 15. this function is enabled w hen external bus is enabled. 40 to 43 p20 to p23 g general purpose i/o ports. the register can be set to select whether to use a pull-up resistor. in external bus m ode, the pins are enabled as a general- purpose i/o port when the corresponding bit in the external address output control register (hacr) is 1. a16 to a19 output pins for a16 to a19 of the external address data bus. when the corresponding bit in the exte rnal address output control register (hacr) is 0, the pins are enabled as high address output pins a16 to a19. ppg9 (8) , ppgb (a) , ppgd (c) , ppgf (e) output pins for ppgs 44 p24 g general purpose i/o port. the register can be set to select whether to use a pull-up resistor. in external bus m ode, the pin is enabled as a general- purpose i/o port when the corresponding bit in the external address output control register (hacr) is 1. a20 output pin for a20 of the external address data bus. when the correspond- ing bit in the external address output cont rol register (hacr) is 0, the pin is enabled as high address output pin a20. in0 data sample input pin for input capture icu0 51 p25 g general purpose i/o port. the register can be set to select whether to use a pull-up resistor. in external bus m ode, the pin is enabled as a general- purpose i/o port when the corresponding bit in the external address output control register (hacr) is 1. a21 output pin for a21 of the external address data bus. when the correspond- ing bit in the external address output cont rol register (hacr) is 0, the pin is enabled as high address output pin a21. in1 data sample input pin for input capture icu1 adtg trigger input pin for a/d converter 52 p44 h general purpose i/o port sda0 serial data i/o pin for i 2 c 0 frck0 input pin for the 16-bit i/o timer 0 53 p45 h general purpose i/o port scl0 serial clock i/o pin for i 2 c 0 frck1 input pin for the 16-bit i/o timer 1
mb90350e series 18 (continued) pin no. pin name i/o circuit type* function 54 p30 g general purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ale address latch enable output pin. this function is enabled when external bus is enabled. in4 data sample input pin for input capture icu4 55 p31 g general purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. rd read strobe output pin for data bus. this function is enabled when external bus is enabled. in5 data sample input pin for input capture icu5 56 p32 g general purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is enabl ed either in single-chip mode or with the wr /wrl pin output disabled. wr /wrl write strobe output pin for the data bu s. this function is enabled when both the external bus and the wr /wr l pin output are enabled. wrl is used to write-strobe 8 lower bits of th e data bus in 16-bit access. wr is used to write-strobe 8 bits of the data bus in 8-bit access. int10r external interrupt request input pin for int10 57 p33 g general purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is en abled either in single-chip mode, in external bus 8-bit mode or with the wrh pin output disabled. wrh write strobe output pin for the 8 higher bi ts of the data bus. this function is enabled when the external bus is en abled, when the external bus 16-bit mode is selected, and when the wrh output pin is enabled. 58 p34 g general purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is enabl ed either in single-chip mode or with the hold function disabled. hrq hold request input pin. this function is enabled when both the external bus and the hold function are enabled. out4 wave form output pi n for output compare ocu4 59 p35 g general purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is enabl ed either in single-chip mode or with the hold function disabled. hak hold acknowledge output pin. this function is enabled when both the external bus and the hol d function are enabled. out5 wave form output pi n for output compare ocu5 60 p36 g general purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is enabl ed either in single-chip mode or with the external ready function disabled. rdy ready input pin. this function is enabled when both the external bus and the external ready function are enabled. out6 wave form output pi n for output compare ocu6
mb90350e series 19 (continued) * : for the i/o circuit type, refer to ? i/o circuit type?. pin no. pin name i/o circuit type* function 61 p37 g general purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is enabl ed either in single-chip mode or with the clk output disabled. clk clk output pin. this function is enabled when both the external bus and clk output are enabled. out7 wave form output pi n for output compare ocu7 62, 63 p60, p61 i general purpose i/o ports an0, an1 analog input pins for a/d converter 64 av cc kv cc power input pin for analog circuits 2 avrh l reference voltage input for the a/d co nverter. this power supply must be turned on or off while a voltage higher than or equal to avrh is applied to av cc . 1av ss kv ss power input pin for analog circuits 22, 23 md1, md0 c input pins for specifying the operating mode 21 md2 d input pin for specifying the operating mode 49 v cc ? power (3.5 v to 5.5 v) input pin 18, 48 v ss ? power (0 v) input pins 50 c k this is the power supply stabilization c apacitor pin. it should be connected to a higher than or equal to 0.1 f ceramic capacitor.
mb90350e series 20 i/o circuit type (continued) type circuit remarks a oscillation circuit high-speed oscillation feedback resistor = approx. 1 m ? b oscillation circuit low-speed oscillation feedback resistor = approx. 10 m ? c mask rom device cmos hysteresis input pin flash memory device cmos input pin d mask rom device cmos hysteresis input pin pull-down resistor value: approx. 50 k ? flash memory device cmos input pin no pull-down e cmos hysteresis input pin pull-up resistor value: approx. 50 k ? standby control signal x1 x0 xout standby control signal x1a x0a xout cmos hysteresis inputs r pull-down resistor cmos hysteresis inputs r pull-up resistor cmos hysteresis inputs r
mb90350e series 21 (continued) type circuit remarks f cmos level output (i ol = 4 ma, i oh = ? 4 ma) cmos hysteresis inputs (with input shutdown function when is standby) automotive input (with the standby-time input shutdown function) g cmos level output (i ol = 4 ma, i oh = ? 4 ma) cmos hysteresis inputs (with the stand- by-time input shutdown function) automotive input (with the standby-time input shutdown function) ttl input (with the standby-time input shutdown function) programmable pull-up resistor: approx. 50 k ? h cmos level output (i ol = 3 ma, i oh = ? 3 ma) cmos hysteresis inputs (with the stand- by-time input shutdown function) automotive input (with the standby-time input shutdown function) cmo s hy s tere s i s inp u t s a u tomotive inp u t s s t a nd b y control for inp u t s h u tdown po u t no u t r p-ch n-ch pull-up control cmos hysteresis inputs automotive inputs ttl input standby control for input shutdown pull-up resistor pout nout r p-ch p-ch n-ch cmos hysteresis inputs automotive inputs standby control for input shutdown pout nout r p-ch n-ch
mb90350e series 22 (continued) type circuit remarks i cmos level output (i ol = 4 ma, i oh = ? 4 ma) cmos hysteresis inputs (with the stand- by-time input shutdown function) automotive input (with the standby-time input shutdown function) analog input for a/d converter k protection circuit for power supply input l with the protection circuit of a/d converter reference voltage power input pin flash memory devices do not have a protection circuit against v cc for pin avrh. cmos hysteresis inputs automotive inputs standby control for input shutdown analog input pout nout r p-ch n-ch p-ch n-ch ane avr ane p-ch n-ch
mb90350e series 23 (continued) type circuit remarks n cmos level output (i ol = 4 ma, i oh = ? 4 ma) cmos inputs (with the standby-time input shutdown function) automotive input (with the standby-time input shutdown function) ttl input (with the standby-time input shutdown function) programmable pull-up resistor: approx. 50 k ? o cmos level output (i ol = 4 ma, i oh = ? 4 ma) cmos inputs (with the standby-time input shutdown function) automotive input (with the standby-time input shutdown function) analog input for a/d converter p u ll- u p control cmo s inp u t s a u tomotive inp u t s ttl inp u t s t a nd b y control for inp u t s h u tdown p u ll- u p re s i s tor po u t no u t r p-ch n-ch p-ch cmos inputs automotive inputs standby control for input shutdown analog input p-ch n-ch pout nout r
mb90350e series 24 handling devices 1. preventing latch-up cmos ic chips may suffer latch - up under the following conditions : ? a voltage higher than v cc or lower than v ss is applied to an input or output pin. a voltage higher than the rate d voltage is applied between v cc and v ss pins. the av cc power supply is applied before the v cc voltage. latch-up may increase the power supply current dras tically, causing thermal damage to the device. for the same reason, also be careful not to let the analog power-supply voltage (av cc , avrh) exceed the digital power-supply voltage (v cc ) . 2. treatment of unused pins leaving unused input pins open may result in misbehav ior or latch up and possib le permanent damage of the device. therefore they must be pulled up or pulled down through resistors. in this case those resistors should be more than 2 k ? . unused i/o pins should be set to the output state and c an be left open, or the input state with the above described connection. 3. using external clock to use external clock, drive the x0 pin and leave x1 pin open. 4. precautions for when not using a sub clock signal x0a and x1a are oscillation pins for sub clock. if you do not connect pins x0a and x1a to an oscillator, use pull-down handling on the x0a pi n, and leave the x1a pin open. 5. notes on during operation of pll clock mode on this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while the pll clock mode is selected, a self-oscillator circuit contained in the pll may c ontinue its operation at its self-running frequency. however, fujitsu will not guaran tee results of operations if such failure occurs. x0 x1 mb90350e series open
mb90350e series 25 6. treatment of power supply pins (v cc /v ss ) if there are multiple v cc and v ss pins, from the point of view of device design, pins to be of the same potential are connected inside of the device to prevent malfunction such as latch-up. to reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level, and observe the standard for total output current, be sure to connect the v cc and v ss pins to the power supply and ground externally. connect v cc and v ss pins to the device from the current supply source at a possibly low impedance. as a measure against power supply noise, it is recommended to connect a capacitor of about 0.1 f as a bypass capacitor between v cc and v ss pins in the vicinity of v cc and v ss pins of the device. 7. pull-up/down resistors the mb90350e series does not support internal pull-up/down resistors (port 0 to port 3: built-in pull-up resistors). use external components where needed. 8. crystal oscillator circuit noise around the x0/x1, or x0a/x1a pins may cause this device to operate abnormally. in the interest of stable operation it is strongly recommended that printed circui t artwork places ground bypass capacitors as close as possible to the x0/x1, x0a/x1a and crystal oscillator (or ceramic oscillator) and that oscillator lines do not cross the lines of other circuits. please ask each crystal maker to ev aluate the oscillational characteristi cs of the crystal and this device. 9. turning-on sequence of power supply to a/d converter and analog inputs make sure to turn on the a/d converter power supply (av cc , avrh) and analog inputs (an0 to an14) after turning-on the digital power supply (v cc ) .turn-off the digital power after turning off the a/d converter power supply and analog inputs. in this case, make sure that the voltage does not exceed avrh or av cc (turning on/ off the analog and digital power supplies simultaneously is acceptable). 10. connection of unused pins of a/d converter if a/d converter is not used connect unused pins of a/d converter to av cc = v cc , av ss = avrh = v ss . 11. notes on energization to prevent the internal regulator ci rcuit from malfunctioning, set the vo ltage rise time during energization at 50 s or more (0.2 v to 2.7 v) . vcc vss vss vcc vss vcc mb90350e series vcc vss vcc vss
mb90350e series 26 12. stabilization of power supply voltage a sudden change in the power supply voltage may cause the device to malfunction even within the specified power supply voltage v cc operating range. therefore, the power supply voltage v cc should be stabilized. for reference, the power supply voltag e should be controlled so that v cc ripple variations (peak-to-peak value) at commercial frequencies (50 hz/60 hz) fall below 10 % of the standard power supply voltage v cc and the coefficient of fluctuation does not exceed 0.1 v/ms at instantaneous power switching. 13. initialization in the device, there are internal registers which are in itialized only by a power-on reset. to initialize these registers, turn on the power again. 14. port 0 to port 3 output during power-on (external-bus mode) as shown below, when power is turned on in external-b us mode, there is a possib ility that output signal of port 0 to port 3 might be unstable regardless of reset inputs. 15. setting using can function to use can function, please set ?1? to dire ct bit of can direct mode register (cdmr). if direct bit is set to ?0? (initial value), wa it states will be performed when accessing can registers. note : please refer to section ?23.12 can direct mode r egister? in hardware manual of mb90350e series for detail of can direct mode register. 16. flash security function the security byte is located in the area of the flash memory. if protection code 01 h is written in the security byte, the flash memory is in the protected state by security. therefore please do not write 01 h in this address if you do not use the security function. please refer to following table for the address of the security byte. 17. operation with t a = + 105 c or more if used exceeding t a = + 105 c, please contact fujitsu sales representatives for reliability limitations. product name flash memory size address for security bit mb90f352e(s) mb90f352te(s) mb90f357e(s) mb90f357te(s) embedded 1 mbit flash memory fe0001 h port 0 to port 3 port 0 to port 3 o u tp u t s might b e u n s t ab le. port 0 to port 3 o u tp u t s = hi-z v cc 1/2 v cc
mb90350e series 27 18. low voltage/cpu operation reset circuit the low voltage detection reset circuit is a function that monitors power supply voltage in order to detect when a voltage drops below a given voltage level. when a lo w voltage condition is detected, an internal reset signal is generated. the cpu operation detection reset circuit is a 20-bit counter that uses oscillation as a count clock and generates an internal reset signal if not clea red within a given time after startup. (1) low voltage detection reset circuit when a low voltage condition is detected, the low vo ltage detection flag (lvrc : lvrf) is set to ?1? and an internal reset signal is output. because the low voltage detection reset circuit continues to operate even in stop mode, detection of a low voltage condition generates an internal reset and releases stop mode. during an internal ram write cycle, low voltage reset is generated after the completion of writing. during the output of this internal reset, the reset output from the low voltage detection reset circuit is suppressed. (2) cpu operation detection reset circuit the cpu operation detection reset circuit is a counte r that prevents program runaway. the counter starts automatically after a power-on reset, and must be cont inually and regularly cleared within a given time. if the given time interval elapses and the counter has not been cleared, a cause su ch as infinite program looping is assumed and an internal reset signal is generated. the in ternal reset generated from the cpu operation detection circuit has a width of 5 machine cycles. * : this value assumes the interval time at an oscillation clock frequency of 4 mhz. during recovery from standby mode, the detect ion period is the maximum interval plus 20 s. this circuit does not operate in m odes where cpu operation is stopped. the cpu operation detection reset circuit counter is cleared under any of the following conditions. ?0? writing to cl bit of lvrc register internal reset main oscillation clock stop transit to sleep mode transit to timebase timer mode and watch mode 19. internal cr oscillation circuit detection voltage 4.0 v 0.3 v interval time 2 20 /f c (approx. 262 ms*) parameter symbol value unit min typ max oscillation frequency f rc 50 100 200 khz oscillation stabilization wait time tstab ?? 100 s
mb90350e series 28 block diagrams ? mb90v340e-101/102 av cc scl0,scl1 sda0,sda1 ppgf to ppg0 da00,da01 adtg avrh avrl an2 3 to an0 av ss sin4 to sin0 sck4 to sck0 sot4 to sot0 x0 x0a* frck0 in7 to in0 out7 to out0 frck1 rx2 to rx0 tx2 to tx0 tin 3 to tin0 tot 3 to tot0 ad15 to ad00 a21 to a16 ale rd wr/wrl wrh hrq hak rdy clk int15 to int 8 int7 to int0 ckot (int11r to int9r) rst x1 x1a* clock controller ram 30 kbytes prescaler 5 channels uart 5 channels i/o timer 0 input capture 8 channels output compare 8 channels i/o timer 1 can controller 3 channels 16-bit reload timer 4 channels 8/10-bit a/d converter 24 channels 10-bit d/a converter 2 channels 8/16-bit ppg 16 channels i 2 c interface 2 channels dtp/ external interrupt external bus interface f 2 mc-16lx bus * : mb90v340e-102 only clock monitor dmac f 2 mc-16lx cpu
mb90350e series 29 mb90v340e-103/104 av cc scl1, scl0 sda1, sda0 ppgf to ppg0 da01, da00 adtg avrh an2 3 to an0 av ss sin4 to sin0 sck4 to sck0 sot4 to sot0 x0 x0a* frck0 in7 to in0 out7 to out0 frck1 rx2 to rx0 tx2 to tx0 tin 3 to tin0 tot 3 to tot0 ad15 to ad00 a2 3 to a16 ale hrq rdy clk int15 to int 8 (int15r to int 8 r) rst dma hak wrh wrl rd avrl ckot int7 to int0 x1 x1a* clock controller/ monitor cr oscillation circuit uart 5 channels i/o timer 0 input capture 8 channels output compare 8 channels i/o timer 1 can controller 3 channels 16-bit reload timer 4 channels 8/10-bit a/d converter 24 channels 10-bit d/a converter 2 channels 8/16-bit ppg 16 channels i 2 c interface 2 channels dtp/external interrupt external bus interface f 2 mc-16lx bus * : mb90v340e-104 only clock monitor ram 30 kbytes prescaler 5 channels f 2 mc-16lx cpu
mb90350e series 30 mb90f352e ( s ) , mb90f352te ( s ) , mb90f351e ( s ) , mb90f351te ( s ) , mb90352e ( s ) , mb90352te ( s ) , mb90351e ( s ) , mb90351te ( s ) av cc scl0 sda0 ppg6, ppg4 ppgf to ppg 8 adtg avrh an14 to an0 av ss sin 3 , sin2 sck 3 , sck2 sot 3 , sot2 frck0 in7 to in4, in1, in0 out7 to out4 frck1 rx1 tx1 tin 3 , tin1 tot 3 , tot1 ad15 to ad00 a21 to a16 ale rd wr/wrl wrh hrq hak rdy clk int15 to int 8 (int11r to int9r) dmac x0 x0a * 1 rst x1 x1a* 1 clock controller low voltage/ cpu operation detection reset * 2 prescaler 2 channels uart 2 channels i/o timer 0 input capture 6 channels output compare 4 channels i/o timer 1 can controller 1 channel 16-bit reload timer 2 channels 8/10-bit a/d converter 15 channels 8/16-bit ppg 10/6 channels i 2 c interface 1 channel dtp/ external interrupt external bus interface f 2 mc-16lx bus * 1 : only for devices without ? s ?-suffix * 2 : only for devices with ?t?-suffix ram 4 kbytes rom/flash 128 kbytes/ 64 kbytes f 2 mc-16lx cpu
mb90350e series 31 ? mb90f357e (s) , mb90f357te (s) , mb90f356e (s) , mb90f356te (s) , mb90357e (s) , mb90357te (s) , mb90356e (s) , mb90356te (s) av cc s cl0 s da0 ppg6, ppg4 ppgf to ppg8 adtg avrh an14 to an0 av ss s in 3 , s in2 s ck 3 , s ck2 s ot 3 , s ot2 x0 x0a* 1 r s t frck0 in7 to in4, in1, in0 out7 to out4 frck1 rx1 tx1 tin 3 , tin1 tot 3 , tot1 ad15 to ad00 a21 to a16 ale rd wr/wrl wrh hrq hak rdy clk int15 to int8 (int11r to int9r) dmac x1 x1a* 1 clock controller/ monitor cr oscillation circuit prescaler 2 channels uart 2 channels i/o timer 0 input capture 6 channels output compare 4 channels i/o timer 1 can controller 1 channel 16-bit reload timer 4 channels 8 /10-bit a/d converter 15 channels 8 /16-bit ppg 10/6 channels i 2 c interface 1 channel external interrupt external bus interface * 1 : only for devices without ?s?-suffix * 2 : only for devices with ?t?-suffix ram 4 kbytes rom/flash 12 8 kbytes/ 64 kbytes low voltage/ cpu operation detector reset * 2 f 2 mc-16lx bus f 2 mc-16lx cpu
mb90350e series 32 memory map note : the high-order portion of bank 00 gives the image of the ff bank rom to make the small model of the c compiler effective. since the low-order 16 bits are the same, the table in rom can be referenced without using the far specification in the pointer declaration. for example, an attempt to access 00c000 h practically accesses the value at ffc000 h in rom. the rom area in bank ff exceeds 32 kbytes, an d its entire image cannot be shown in bank 00. the image between ff8000 h and ffffff h is visible in bank 00, while the image between ff0000 h and ff7fff h is visible only in bank ff. mb90 3 51e ( s ) mb90 3 51te ( s ) mb90f 3 51e ( s ) mb90f 3 51te ( s ) mb90 3 56e ( s ) mb90 3 56te ( s ) mb90f 3 56e ( s ) mb90f 3 56te ( s ) mb90 3 52e ( s ) mb90 3 52te ( s ) mb90f 3 52e ( s ) mb90f 3 52te ( s ) mb90 3 57e ( s ) mb90 3 57te ( s ) mb90f 3 57e ( s ) mb90f 3 57te ( s ) mb90v 3 40e-101 mb90v 3 40e-102 mb90v 3 40e-10 3 mb90v 3 40e-104 ffffff h f90000 h f9ffff h fa0000 h faffff h fb0000 h fbffff h fc0000 h fcffff h fd0000 h fdffff h fe0000 h feffff h ff0000 h f 8 ffff h f 8 0000 h 00ffff h 00 8 000 h 007fff h 007900 h 007 8 ff h 000100 h 0000ef h 000000 h ffffff h c00100 h fdffff h fe0000 h feffff h ff0000 h 00ffff h 007fff h 00 8 000 h 007900 h 001100 h 0010ff h 000100 h 0000ef h 000000 h ffffff h c00100 h fdffff h ff0000 h 00ffff h 007fff h 00 8 000 h 007900 h 001100 h 0010ff h 000100 h 0000ef h 000000 h rom (ff bank) rom (fe bank) rom (fd bank) rom (fc bank) rom (fb bank) rom (fa bank) rom (f9 bank) rom (f8 bank) rom (image of ff bank) peripheral ram 30 kbytes rom (ff bank) rom (fe bank) external access area ram 4 kbytes rom (ff bank) peripheral peripheral rom (image of ff bank) peripheral external ac cess area external access area rom (image of ff bank) peripheral ram 4 kbytes external access area peripheral : no access external ac cess area external access area
mb90350e series 33 i/o map (continued) address register abbreviation access resource name initial value 000000 h port 0 data register pdr0 r/w port 0 xxxxxxxx b 000001 h port 1 data register pdr1 r/w port 1 xxxxxxxx b 000002 h port 2 data register pdr2 r/w port 2 xxxxxxxx b 000003 h port 3 data register pdr3 r/w port 3 xxxxxxxx b 000004 h port 4 data register pdr4 r/w port 4 xxxxxxxx b 000005 h port 5 data register pdr5 r/w port 5 xxxxxxxx b 000006 h port 6 data register pdr6 r/w port 6 xxxxxxxx b 000007 h to 00000a h reserved 00000b h port 5 analog input enable regist er ader5 r/w port 5, a/d 11111111 b 00000c h port 6 analog input enable regist er ader6 r/w port 6, a/d 11111111 b 00000d h reserved 00000e h input level select register 0 ilsr0 r/w ports 00000000 b 00000f h input level select register 1 ilsr1 r/w ports 00000000 b 000010 h port 0 direction register ddr0 r/w port 0 00000000 b 000011 h port 1 direction register ddr1 r/w port 1 00000000 b 000012 h port 2 direction register ddr2 r/w port 2 xx000000 b 000013 h port 3 direction register ddr3 r/w port 3 00000000 b 000014 h port 4 direction register ddr4 r/w port 4 xx000000 b 000015 h port 5 direction register ddr5 r/w port 5 x0000000 b 000016 h port 6 direction register ddr6 r/w port 6 00000000 b 000017 h to 000019 h reserved 00001a h sin input level setting register ddra w uart2, uart3 x00xxxxx b 00001b h reserved 00001c h port 0 pull-up control register pucr0 r/w port 0 00000000 b 00001d h port 1 pull-up control register pucr1 r/w port 1 00000000 b 00001e h port 2 pull-up control register pucr2 r/w port 2 00000000 b 00001f h port 3 pull-up control register pucr3 r/w port 3 00000000 b 000020 h to 000037 h reserved
mb90350e series 34 (continued) address register abbreviation access resource name initial value 000038 h ppg 4 operation mode control register ppgc4 w, r/w 16-bit programmable pulse generator 4/5 0x000xx1 b 000039 h ppg 5 operation mode control register ppgc5 w, r/w 0x000001 b 00003a h ppg 4/5 count clock select register ppg45 r/w 000000x0 b 00003b h address detect control register 1 pacsr1 r/w address match detection 1 00000000 b 00003c h ppg 6 operation mode control register ppgc6 w, r/w 16-bit programmable pulse generator 6/7 0x000xx1 b 00003d h ppg 7 operation mode control register ppgc7 w, r/w 0x000001 b 00003e h ppg 6/7 count clock select register ppg67 r/w 000000x0 b 00003f h reserved 000040 h ppg 8 operation mode control register ppgc8 w, r/w 16-bit programmable pulse generator 8/9 0x000xx1 b 000041 h ppg 9 operation mode control register ppgc9 w, r/w 0x000001 b 000042 h ppg 8/9 count clock select register ppg89 r/w 000000x0 b 000043 h reserved 000044 h ppg a operation mode control register ppgca w, r/w 16-bit programmable pulse generator a/b 0x000xx1 b 000045 h ppg b operation mode control register ppgcb w, r/w 0x000001 b 000046 h ppg a/b count clock select register ppgab r/w 000000x0 b 000047 h reserved 000048 h ppg c operation mode control register ppgcc w,r/w 16-bit programmable pulse generator c/d 0x000xx1 b 000049 h ppg d operation mode control register ppgcd w,r/w 0x000001 b 00004a h ppg c/d count clock select register ppgcd r/w 000000x0 b 00004b h reserved 00004c h ppg e operation mode control register ppgce w,r/w 16-bit programmable pulse generator e/f 0x000xx1 b 00004d h ppg f operation mode control register ppgcf w,r/w 0x000001 b 00004e h ppg e/f count clock select register ppgef r/w 000000x0 b 00004f h reserved 000050 h input capture control status register 0/1 ics01 r/w input capture 0/1 00000000 b 000051 h input capture edge register 0/1 ice01 r/w, r xxx0x0xx b 000052 h , 000053 h reserved 000054 h input capture control status register 4/5 ics45 r/w input capture 4/5 00000000 b 000055 h input capture edge register 4/5 ice45 r xxxxxxxx b 000056 h input capture control status register 6/7 ics67 r/w input capture 6/7 00000000 b 000057 h input capture edge register 6/7 ice67 r/w, r xxx000xx b
mb90350e series 35 (continued) address register abbreviation access resource name initial value 000058 h to 00005b h reserved 00005c h output compare control status register 4 ocs4 r/w output compare 4/5 0000xx00 b 00005d h output compare control status register 5 ocs5 r/w 0xx00000 b 00005e h output compare control status register 6 ocs6 r/w output compare 6/7 0000xx00 b 00005f h output compare control status register 7 ocs7 r/w 0xx00000 b 000060 h timer control status register 0 tmcsr0 r/w 16-bit reload timer 0 00000000 b 000061 h timer control status register 0 tmcsr0 r/w xxxx0000 b 000062 h timer control status register 1 tmcsr1 r/w 16-bit reload timer 1 00000000 b 000063 h timer control status register 1 tmcsr1 r/w xxxx0000 b 000064 h timer control status register 2 tmcsr2 r/w 16-bit reload timer 2 00000000 b 000065 h timer control status register 2 tmcsr2 r/w xxxx0000 b 000066 h timer control status register 3 tmcsr3 r/w 16-bit reload timer 3 00000000 b 000067 h timer control status register 3 tmcsr3 r/w xxxx0000 b 000068 h a/d control status register 0 adcs0 r/w a/d converter 000xxxx0 b 000069 h a/d control status register 1 adcs1 r/w 0000000x b 00006a h a/d data register 0 adcr0 r 00000000 b 00006b h a/d data register 1 adcr1 r xxxxxx00 b 00006c h adc setting register 0 adsr0 r/w 00000000 b 00006d h adc setting register 1 adsr1 r/w 00000000 b 00006e h low voltage/cpu operation detection reset control register lvrc r/w, w low voltage/cpu operation detection reset 00111000 b 00006f h rom mirror function select register romm w rom mirror xxxxxxx1 b 000070 h to 00007f h reserved 000080 h to 00008f h reserved for can contro ller 1. refer to ? can controllers? 000090 h to 00009a h reserved
mb90350e series 36 (continued) address register abbreviation access resource name initial value 00009b h dma descriptor channel specification register dcsr r/w dma 00000000 b 00009c h dma status register l register dsrl r/w 00000000 b 00009d h dma status register h register dsrh r/w 00000000 b 00009e h address detect control register 0 pacsr0 r/w address match detection 0 00000000 b 00009f h delayed interrupt/release register dirr r/w delayed interrupt xxxxxxx0 b 0000a0 h low-power consumption mode control register lpmcr w,r/w low power consumption control circuit 00011000 b 0000a1 h clock selection register ckscr r,r/w low power consumption control circuit 11111100 b 0000a2 h , 0000a3 h reserved 0000a4 h dma stop status register dssr r/w dma 00000000 b 0000a5 h automatic ready function selection register arsr w external memory access 0011xx00 b 0000a6 h external address output control register hacr w 00000000 b 0000a7 h bus control signal selection register ecsr w 0000000x b 0000a8 h watchdog control register wdtc r,w watchdog timer xxxxx111 b 0000a9 h timebase timer control register tbtc w,r/w timebase timer 1xx00100 b 0000aa h watch timer control register wtc r,r/w watch timer 1x001000 b 0000ab h reserved 0000ac h dma enable register l register derl r/w dma 00000000 b 0000ad h dma enable register h register derh r/w 00000000 b 0000ae h flash control status register (flash devices only. otherwise reserved) fmcs r,r/w flash memory 000x0000 b 0000af h reserved 0000b0 h interrupt control register 00 icr00 w,r/w interrupt control 00000111 b 0000b1 h interrupt control register 01 icr01 w,r/w 00000111 b 0000b2 h interrupt control register 02 icr02 w,r/w 00000111 b 0000b3 h interrupt control register 03 icr03 w,r/w 00000111 b 0000b4 h interrupt control register 04 icr04 w,r/w 00000111 b 0000b5 h interrupt control register 05 icr05 w,r/w 00000111 b 0000b6 h interrupt control register 06 icr06 w,r/w 00000111 b 0000b7 h interrupt control register 07 icr07 w,r/w 00000111 b 0000b8 h interrupt control register 08 icr08 w,r/w 00000111 b
mb90350e series 37 (continued) address register abbreviation access resource name initial value 0000b9 h interrupt control register 09 icr09 w,r/w interrupt control 00000111 b 0000ba h interrupt control register 10 icr10 w,r/w 00000111 b 0000bb h interrupt control register 11 icr11 w,r/w 00000111 b 0000bc h interrupt control register 12 icr12 w,r/w 00000111 b 0000bd h interrupt control register 13 icr13 w,r/w 00000111 b 0000be h interrupt control register 14 icr14 w,r/w 00000111 b 0000bf h interrupt control register 15 icr15 w,r/w 00000111 b 0000c0 h to 0000c9 h reserved 0000ca h external interrupt enable register 1 enir1 r/w external interrupt 1 00000000 b 0000cb h external interrupt source register 1 eirr1 r/w xxxxxxxx b 0000cc h external interrupt level register 1 elvr1 r/w 00000000 b 0000cd h external interrupt level register 1 elvr1 r/w 00000000 b 0000ce h external interrupt source select register eissr r/w 00000000 b 0000cf h pll/sub clock control register psccr w pll xxxx0000 b 0000d0 h dma buffer address pointer l register bapl r/w dma xxxxxxxx b 0000d1 h dma buffer address pointer m register bapm r/w xxxxxxxx b 0000d2 h dma buffer address pointer h register baph r/w xxxxxxxx b 0000d3 h dma control register dmacs r/w xxxxxxxx b 0000d4 h i/o register address pointer l register ioal r/w xxxxxxxx b 0000d5 h i/o register address pointer h register ioah r/w xxxxxxxx b 0000d6 h data counter l register dctl r/w xxxxxxxx b 0000d7 h data counter h register dcth r/w xxxxxxxx b 0000d8 h serial mode register 2 smr2 w,r/w uart2 00000000 b 0000d9 h serial control register 2 scr2 w,r/w 00000000 b 0000da h reception/transmission data register 2 rdr2/tdr2 r/w 00000000 b 0000db h serial status register 2 ssr2 r,r/w 00001000 b 0000dc h extended communication control register 2 eccr2 r,w, r/w 000000xx b 0000dd h extended status/control register 2 escr2 r/w 00000100 b 0000de h baud rate generator register 20 bgr20 r/w 00000000 b
mb90350e series 38 (continued) address register abbreviation access resource name initial value 0000df h baud rate generator register 21 bgr21 r/w uart2 00000000 b 0000e0 h to 0000ef h reserved 0000f0 h to 0000ff h external area 007900 h to 007907 h reserved 007908 h reload register l4 prll4 r/w 16-bit programmable pulse generator 4/5 xxxxxxxx b 007909 h reload register h4 prlh4 r/w xxxxxxxx b 00790a h reload register l5 prll5 r/w xxxxxxxx b 00790b h reload register h5 prlh5 r/w xxxxxxxx b 00790c h reload register l6 prll6 r/w 16-bit programmable pulse generator 6/7 xxxxxxxx b 00790d h reload register h6 prlh6 r/w xxxxxxxx b 00790e h reload register l7 prll7 r/w xxxxxxxx b 00790f h reload register h7 prlh7 r/w xxxxxxxx b 007910 h reload register l8 prll8 r/w 16-bit programmable pulse generator 8/9 xxxxxxxx b 007911 h reload register h8 prlh8 r/w xxxxxxxx b 007912 h reload register l9 prll9 r/w xxxxxxxx b 007913 h reload register h9 prlh9 r/w xxxxxxxx b 007914 h reload register la prlla r/w 16-bit programmable pulse generator a/b xxxxxxxx b 007915 h reload register ha prlha r/w xxxxxxxx b 007916 h reload register lb prllb r/w xxxxxxxx b 007917 h reload register hb prlhb r/w xxxxxxxx b 007918 h reload register lc prllc r/w 16-bit programmable pulse generator c/d xxxxxxxx b 007919 h reload register hc prlhc r/w xxxxxxxx b 00791a h reload register ld prlld r/w xxxxxxxx b 00791b h reload register hd prlhd r/w xxxxxxxx b 00791c h reload register le prlle r/w 16-bit programmable pulse generator e/f xxxxxxxx b 00791d h reload register he prlhe r/w xxxxxxxx b 00791e h reload register lf prllf r/w xxxxxxxx b 00791f h reload register hf prlhf r/w xxxxxxxx b 007920 h input capture register 0 ipcp0 r input capture 0/1 xxxxxxxx b 007921 h input capture register 0 ipcp0 r xxxxxxxx b 007922 h input capture register 1 ipcp1 r xxxxxxxx b 007923 h input capture register 1 ipcp1 r xxxxxxxx b
mb90350e series 39 (continued) address register abbrevia- tion access resource name initial value 007924 h to 007927 h reserved 007928 h input capture register 4 ipcp4 r input capture 4/5 xxxxxxxx b 007929 h input capture register 4 ipcp4 r xxxxxxxx b 00792a h input capture register 5 ipcp5 r xxxxxxxx b 00792b h input capture register 5 ipcp5 r xxxxxxxx b 00792c h input capture register 6 ipcp6 r input capture 6/7 xxxxxxxx b 00792d h input capture register 6 ipcp6 r xxxxxxxx b 00792e h input capture register 7 ipcp7 r xxxxxxxx b 00792f h input capture register 7 ipcp7 r xxxxxxxx b 007930 h to 007937 h reserved 007938 h output compare register 4 occp4 r/w output compare 4/5 xxxxxxxx b 007939 h output compare register 4 occp4 r/w xxxxxxxx b 00793a h output compare register 5 occp5 r/w xxxxxxxx b 00793b h output compare register 5 occp5 r/w xxxxxxxx b 00793c h output compare register 6 occp6 r/w output compare 6/7 xxxxxxxx b 00793d h output compare register 6 occp6 r/w xxxxxxxx b 00793e h output compare register 7 occp7 r/w xxxxxxxx b 00793f h output compare register 7 occp7 r/w xxxxxxxx b 007940 h timer data register 0 tcdt0 r/w i/o timer 0 00000000 b 007941 h timer data register 0 tcdt0 r/w 00000000 b 007942 h timer control status register 0 tccsl0 r/w 00000000 b 007943 h timer control status register 0 tccsh0 r/w 0xxxxxxx b 007944 h timer data register 1 tcdt1 r/w i/o timer 1 00000000 b 007945 h timer data register 1 tcdt1 r/w 00000000 b 007946 h timer control status register 1 tccsl1 r/w 00000000 b 007947 h timer control status register 1 tccsh1 r/w 0xxxxxxx b 007948 h timer register 0/reload register 0 tmr0/ tmrlr0 r/w 16-bit reload timer 0 xxxxxxxx b 007949 h r/w xxxxxxxx b 00794a h timer register 1/reload register 1 tmr1/ tmrlr1 r/w 16-bit reload timer 1 xxxxxxxx b 00794b h r/w xxxxxxxx b 00794c h timer register 2/reload register 2 tmr2/ tmrlr2 r/w 16-bit reload timer 2 xxxxxxxx b 00794d h r/w xxxxxxxx b 00794e h timer register 3/reload register 3 tmr3/ tmrlr3 r/w 16-bit reload timer 3 xxxxxxxx b 00794f h r/w xxxxxxxx b
mb90350e series 40 (continued) address register abbreviation access resource name initial value 007950 h serial mode register 3 smr3 w, r/w uart3 00000000 b 007951 h serial control register 3 scr3 w, r/w 00000000 b 007952 h reception/transmission data register 3 rdr3/tdr3 r/w 00000000 b 007953 h serial status register 3 ssr3 r,r/w 00001000 b 007954 h extended communication control register 3 eccr3 r,w, r/w 000000xx b 007955 h extended status control register 3 escr3 r/w 00000100 b 007956 h baud rate generator register 30 bgr30 r/w 00000000 b 007957 h baud rate generator register 31 bgr31 r/w 00000000 b 007958 h , 007959 h reserved 007960 h clock supervisor control register csvcr r, r/w clock supervisor 00011100 b 007961 h to 00796d h reserved 00796e h can direct mode register cdmr r/w can clock sync xxxxxxx0 b 00796f h reserved 007970 h i 2 c bus status register 0 ibsr0 r i 2 c interface 0 00000000 b 007971 h i 2 c bus control register 0 ibcr0 w,r/w 00000000 b 007972 h i 2 c 10-bit slave address register 0 itbal0 r/w 00000000 b 007973 h itbah0 r/w 00000000 b 007974 h i 2 c 10-bit slave address mask register 0 itmkl0 r/w 11111111 b 007975 h itmkh0 r/w 00111111 b 007976 h i 2 c 7-bit slave address register 0 isba0 r/w 00000000 b 007977 h i 2 c 7-bit slave address mask register 0 ismk0 r/w 01111111 b 007978 h i 2 c data register 0 idar0 r/w 00000000 b 007979 h , 00797a h reserved 00797b h i 2 c clock control register 0 iccr0 r/w i 2 c interface 0 00011111 b 00797c h to 0079a1 h reserved 0079a2 h flash write control register 0 fwr0 r/w dual operation flash 00000000 b 0079a3 h flash write control register 1 fwr1 r/w 00000000 b 0079a4 h sector change setting register 0 ssr0 r/w 00xxxxx0 b 0079a5 h to 0079c1 h reserved 0079c2 h setting prohibited
mb90350e series 41 (continued) notes : ? initial value of ?x? represents unknown value. ? any write access to reserved addresses in i/o map should not be performed. a read access to reserved addresses results reading unknown value. address register abbreviation access resource name initial value 0079c3 h to 0079df h reserved 0079e0 h detect address setting register 0 padr0 r/w address match detection 0 xxxxxxxx b 0079e1 h detect address setting register 0 padr0 r/w xxxxxxxx b 0079e2 h detect address setting register 0 padr0 r/w xxxxxxxx b 0079e3 h detect address setting register 1 padr1 r/w xxxxxxxx b 0079e4 h detect address setting register 1 padr1 r/w xxxxxxxx b 0079e5 h detect address setting register 1 padr1 r/w xxxxxxxx b 0079e6 h detect address setting register 2 padr2 r/w xxxxxxxx b 0079e7 h detect address setting register 2 padr2 r/w xxxxxxxx b 0079e8 h detect address setting register 2 padr2 r/w xxxxxxxx b 0079e9 h to 0079ef h reserved 0079f0 h detect address setting register 3 padr3 r/w address match detection 1 xxxxxxxx b 0079f1 h detect address setting register 3 padr3 r/w xxxxxxxx b 0079f2 h detect address setting register 3 padr3 r/w xxxxxxxx b 0079f3 h detect address setting register 4 padr4 r/w xxxxxxxx b 0079f4 h detect address setting register 4 padr4 r/w xxxxxxxx b 0079f5 h detect address setting register 4 padr4 r/w xxxxxxxx b 0079f6 h detect address setting register 5 padr5 r/w xxxxxxxx b 0079f7 h detect address setting register 5 padr5 r/w xxxxxxxx b 0079f8 h detect address setting register 5 padr5 r/w xxxxxxxx b 0079f9 h to 007bff h reserved 007c00 h to 007dff h reserved for can controller 1. refer to ? can controllers? 007e00 h to 007fff h reserved
mb90350e series 42 can controllers compliant with can standard version2.0 part a and part b - supports transmission/reception in standard frame and extended frame formats supports transmitting of data fram es by receiving remote frames 16 transmitting/receiving message buffers - 29-bit id and 8-byte data - multi-level message buffer configuration provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message buffer as id acceptance mask - two acceptance mask registers in either st andard frame format or extended frame formats bit rate programmable from 10 kbps to 2 mbps (when input clock is at 16 mhz) list of control registers (continued) address register abbreviation access initial value can1 000080 h message buffer enable register bvalr r/w 00000000 b 00000000 b 000081 h 000082 h transmit request register treqr r/w 00000000 b 00000000 b 000083 h 000084 h transmit cancel register tcanr w 00000000 b 00000000 b 000085 h 000086 h transmission complete register tcr r/w 00000000 b 00000000 b 000087 h 000088 h receive complete register rcr r/w 00000000 b 00000000 b 000089 h 00008a h remote request receiving register rrtrr r/w 00000000 b 00000000 b 00008b h 00008c h receive overrun register rovrr r/w 00000000 b 00000000 b 00008d h 00008e h reception interrupt enable register rier r/w 00000000 b 00000000 b 00008f h
mb90350e series 43 (continued) address register abbreviation access initial value can1 007d00 h control status register csr r/w, w r/w, r 0xxxx0x1 b 00xxx000 b 007d01 h 007d02 h last event indicator register leir r/w 000x0000 b xxxxxxxx b 007d03 h 007d04 h receive/transmit error counter rtec r 00000000 b 00000000 b 007d05 h 007d06 h bit timing register btr r/w 11111111 b x1111111 b 007d07 h 007d08 h ide register ider r/w xxxxxxxx b xxxxxxxx b 007d09 h 007d0a h transmit rtr register trtrr r/w 00000000 b 00000000 b 007d0b h 007d0c h remote frame receive waiting register rfwtr r/w xxxxxxxx b xxxxxxxx b 007d0d h 007d0e h transmit interrupt enable register tier r/w 00000000 b 00000000 b 007d0f h 007d10 h acceptance mask select register amsr r/w xxxxxxxx b xxxxxxxx b 007d11 h 007d12 h xxxxxxxx b xxxxxxxx b 007d13 h 007d14 h acceptance mask register 0 amr0 r/w xxxxxxxx b xxxxxxxx b 007d15 h 007d16 h xxxxxxxx b xxxxxxxx b 007d17 h 007d18 h acceptance mask register 1 amr1 r/w xxxxxxxx b xxxxxxxx b 007d19 h 007d1a h xxxxxxxx b xxxxxxxx b 007d1b h
mb90350e series 44 list of message buffers (id registers) (continued) address register abbreviation access initial value can1 007c00 h to 007c1f h general-purpose ram ? r/w xxxxxxxx b to xxxxxxxx b 007c20 h id register 0 idr0 r/w xxxxxxxx b xxxxxxxx b 007c21 h 007c22 h xxxxxxxx b xxxxxxxx b 007c23 h 007c24 h id register 1 idr1 r/w xxxxxxxx b xxxxxxxx b 007c25 h 007c26 h xxxxxxxx b xxxxxxxx b 007c27 h 007c28 h id register 2 idr2 r/w xxxxxxxx b xxxxxxxx b 007c29 h 007c2a h xxxxxxxx b xxxxxxxx b 007c2b h 007c2c h id register 3 idr3 r/w xxxxxxxx b xxxxxxxx b 007c2d h 007c2e h xxxxxxxx b xxxxxxxx b 007c2f h 007c30 h id register 4 idr4 r/w xxxxxxxx b xxxxxxxx b 007c31 h 007c32 h xxxxxxxx b xxxxxxxx b 007c33 h 007c34 h id register 5 idr5 r/w xxxxxxxx b xxxxxxxx b 007c35 h 007c36 h xxxxxxxx b xxxxxxxx b 007c37 h 007c38 h id register 6 idr6 r/w xxxxxxxx b xxxxxxxx b 007c39 h 007c3a h xxxxxxxx b xxxxxxxx b 007c3b h 007c3c h id register 7 idr7 r/w xxxxxxxx b xxxxxxxx b 007c3d h 007c3e h xxxxxxxx b xxxxxxxx b 007c3f h
mb90350e series 45 (continued) address register abbreviation access initial value can1 007c40 h id register 8 idr8 r/w xxxxxxxx b xxxxxxxx b 007c41 h 007c42 h xxxxxxxx b xxxxxxxx b 007c43 h 007c44 h id register 9 idr9 r/w xxxxxxxx b xxxxxxxx b 007c45 h 007c46 h xxxxxxxx b xxxxxxxx b 007c47 h 007c48 h id register 10 idr10 r/w xxxxxxxx b xxxxxxxx b 007c49 h 007c4a h xxxxxxxx b xxxxxxxx b 007c4b h 007c4c h id register 11 idr11 r/w xxxxxxxx b xxxxxxxx b 007c4d h 007c4e h xxxxxxxx b xxxxxxxx b 007c4f h 007c50 h id register 12 idr12 r/w xxxxxxxx b xxxxxxxx b 007c51 h 007c52 h xxxxxxxx b xxxxxxxx b 007c53 h 007c54 h id register 13 idr13 r/w xxxxxxxx b xxxxxxxx b 007c55 h 007c56 h xxxxxxxx b xxxxxxxx b 007c57 h 007c58 h id register 14 idr14 r/w xxxxxxxx b xxxxxxxx b 007c59 h 007c5a h xxxxxxxx b xxxxxxxx b 007c5b h 007c5c h id register 15 idr15 r/w xxxxxxxx b xxxxxxxx b 007c5d h 007c5e h xxxxxxxx b xxxxxxxx b 007c5f h
mb90350e series 46 list of message buffers (dlc registers and data registers) (continued) address register abbreviation access initial value can1 007c60 h dlc register 0 dlcr0 r/w xxxxxxxx b 007c61 h 007c62 h dlc register 1 dlcr1 r/w xxxxxxxx b 007c63 h 007c64 h dlc register 2 dlcr2 r/w xxxxxxxx b 007c65 h 007c66 h dlc register 3 dlcr3 r/w xxxxxxxx b 007c67 h 007c68 h dlc register 4 dlcr4 r/w xxxxxxxx b 007c69 h 007c6a h dlc register 5 dlcr5 r/w xxxxxxxx b 007c6b h 007c6c h dlc register 6 dlcr6 r/w xxxxxxxx b 007c6d h 007c6e h dlc register 7 dlcr7 r/w xxxxxxxx b 007c6f h 007c70 h dlc register 8 dlcr8 r/w xxxxxxxx b 007c71 h 007c72 h dlc register 9 dlcr9 r/w xxxxxxxx b 007c73 h 007c74 h dlc register 10 dlcr10 r/w xxxxxxxx b 007c75 h 007c76 h dlc register 11 dlcr11 r/w xxxxxxxx b 007c77 h 007c78 h dlc register 12 dlcr12 r/w xxxxxxxx b 007c79 h 007c7a h dlc register 13 dlcr13 r/w xxxxxxxx b 007c7b h 007c7c h dlc register 14 dlcr14 r/w xxxxxxxx b 007c7d h 007c7e h dlc register 15 dlcr15 r/w xxxxxxxx b 007c7f h
mb90350e series 47 (continued) address register abbreviation access initial value can1 007c80 h to 007c87 h data register 0 (8 bytes) dtr0 r/w xxxxxxxx b to xxxxxxxx b 007c88 h to 007c8f h data register 1 (8 bytes) dtr1 r/w xxxxxxxx b to xxxxxxxx b 007c90 h to 007c97 h data register 2 (8 bytes) dtr2 r/w xxxxxxxx b to xxxxxxxx b 007c98 h to 007c9f h data register 3 (8 bytes) dtr3 r/w xxxxxxxx b to xxxxxxxx b 007ca0 h to 007ca7 h data register 4 (8 bytes) dtr4 r/w xxxxxxxx b to xxxxxxxx b 007ca8 h to 007caf h data register 5 (8 bytes) dtr5 r/w xxxxxxxx b to xxxxxxxx b 007cb0 h to 007cb7 h data register 6 (8 bytes) dtr6 r/w xxxxxxxx b to xxxxxxxx b 007cb8 h to 007cbf h data register 7 (8 bytes) dtr7 r/w xxxxxxxx b to xxxxxxxx b 007cc0 h to 007cc7 h data register 8 (8 bytes) dtr8 r/w xxxxxxxx b to xxxxxxxx b 007cc8 h to 007ccf h data register 9 (8 bytes) dtr9 r/w xxxxxxxx b to xxxxxxxx b 007cd0 h to 007cd7 h data register 10 (8 bytes) dtr10 r/w xxxxxxxx b to xxxxxxxx b 007cd8 h to 007cdf h data register 11 (8 bytes) dtr11 r/w xxxxxxxx b to xxxxxxxx b 007ce0 h to 007ce7 h data register 12 (8 bytes) dtr12 r/w xxxxxxxx b to xxxxxxxx b 007ce8 h to 007cef h data register 13 (8 bytes) dtr13 r/w xxxxxxxx b to xxxxxxxx b
mb90350e series 48 (continued) address register abbreviation access initial value can1 007cf0 h to 007cf7 h data register 14 (8 bytes) dtr14 r/w xxxxxxxx b to xxxxxxxx b 007cf8 h to 007cff h data register 15 (8 bytes) dtr15 r/w xxxxxxxx b to xxxxxxxx b
mb90350e series 49 interrupt factors, interrupt vectors, interrupt control register (continued) interrupt cause ei 2 os corresponding dma ch number interrupt vector interrupt control register number address number address reset n ? #08 ffffdc h ?? int9 instruction n ? #09 ffffd8 h ?? exception n ? #10 ffffd4 h ?? reserved n ? #11 ffffd0 h icr00 0000b0 h reserved n ? #12 ffffcc h can 1 rx / input capture 6 y1 ? #13 ffffc8 h icr01 0000b1 h can 1 tx/ns / input capture 7 y1 ? #14 ffffc4 h i 2 cn ? #15 ffffc0 h icr02 0000b2 h reserved n ? #16 ffffbc h 16-bit reload timer 0 y1 0 #17 ffffb8 h icr03 0000b3 h 16-bit reload timer 1 y1 1 #18 ffffb4 h 16-bit reload timer 2 y1 2 #19 ffffb0 h icr04 0000b4 h 16-bit reload timer 3 y1 ? #20 ffffac h ppg 4/5 n ? #21 ffffa8 h icr05 0000b5 h ppg 6/7 n ? #22 ffffa4 h ppg 8/9/c/d n ? #23 ffffa0 h icr06 0000b6 h ppg a/b/e/f n ? #24 ffff9c h timebase timer n ? #25 ffff98 h icr07 0000b7 h external interrupt 8 to 11 y1 3 #26 ffff94 h watch timer n ? #27 ffff90 h icr08 0000b8 h external interrupt 12 to 15 y1 4 #28 ffff8c h a/d converter y1 5 #29 ffff88 h icr09 0000b9 h i/o timer 0 / i/o timer 1 n ? #30 ffff84 h input capture 4/5 y1 6 #31 ffff80 h icr10 0000ba h output compare 4/5 y1 7 #32 ffff7c h input capture 0/1 y1 8 #33 ffff78 h icr11 0000bb h output compare 6/7 y1 9 #34 ffff74 h reserved n 10 #35 ffff70 h icr12 0000bc h reserved n 11 #36 ffff6c h uart 3 rx y2 12 #37 ffff68 h icr13 0000bd h uart 3 tx y1 13 #38 ffff64 h
mb90350e series 50 (continued) y1 : usable y2 : usable, with ei 2 os stop function n : unusable notes : ? the peripheral resources sharing the icr re gister have the same interrupt level. ? when the peripheral resources shar ing the icr register use extended intelligent i/o service, only one can use ei 2 os at a time. ? when either of the two peripheral resource s sharing the icr register specifies ei 2 os, the other one cannot use interrupts. interrupt cause ei 2 os corresponding dma ch number interrupt vector interrupt control register number address number address uart 2 rx y2 14 #39 ffff60 h icr14 0000be h uart 2 tx y1 15 #40 ffff5c h flash memory n ? #41 ffff58 h icr15 0000bf h delayed interrupt n ? #42 ffff54 h
mb90350e series 51 electrical characteristics 1. absolute maximum ratings (continued) parameter symbol rating unit remarks min max power supply voltage* 1 v cc v ss ? 0.3 v ss + 6.0 v av cc v ss ? 0.3 v ss + 6.0 v v cc = av cc * 2 avrh v ss ? 0.3 v ss + 6.0 v av cc avrh* 2 input voltage* 1 v i v ss ? 0.3 v ss + 6.0 v *3 output voltage* 1 v o v ss ? 0.3 v ss + 6.0 v *3 maximum clamp current i clamp ? 4.0 + 4.0 ma *5 total maximum clamp current |i clamp | ? 40 ma *5 ?l? level maximum output current i ol ? 15 ma *4 ?l? level average output current i olav ? 4ma*4 ?l? level maximum overall output current i ol ? 100 ma *4 ?l? level average overall output current i olav ? 50 ma *4 ?h? level maximum output current i oh ?? 15 ma *4 ?h? level average output current i ohav ?? 4ma*4 ?h? level maximum overall output current i oh ?? 100 ma *4 ?h? level average overall output current i ohav ?? 50 ma *4 power consumption p d ? 320 mw operating temperature t a ? 40 + 105 c ? 40 + 125 c*6 storage temperature t stg ? 55 + 150 c
mb90350e series 52 (continued) *1: this parameter is based on v ss = av ss = 0 v *2: set av cc and v cc to the same voltage. make sure that av cc does not exceed v cc and that the voltage at the analog inputs does not exceed av cc when the power is switched on. *3: v i and v o should not exceed v cc + 0.3 v. v i should not exceed the specified ratings. however if the maximum current to/from an input is limited by some means with external components, the i clamp rating supersedes the v i rating. *4: applicable to pins: p00 to p07, p10 to p17, p20 to p25, p30 to p37, p40 to p4 5, p50 to p56, p60 to p67 *5: ? applicable to pins: p00 to p07, p10 to p1 7, p20 to p25, p30 to p37, p40 to p45, p50 to p56 (for evaluation device : p50 to p55) , p60 to p67 ? use within recommended operating conditions. ? use at dc voltage (current) ? the + b signal should always be applied a co nnecting limit resistance between the + b signal and the microcontroller. ? the value of the limiting resistance should be set so that when the + b signal is applied the input current to the microcontroller pin does not exceed rated values, either instan taneously or for prolonged periods. ? note that when the microcontroller drive current is low, such as in the power saving modes, the + b input potential may pass through the protective di ode and increase the potential at the v cc pin, and this may affect other devices. ? note that if a + b signal is input when the microc ontroller power supply is off (n ot fixed at 0 v) , the power supply is provided from the pins, so t hat incomplete operation may result. ? note that if the + b input is applied during power-on, the power supply is provided from the pins and the resulting power supply voltage may not be suffici ent to operate the power-on reset. ? care must be taken not to leave the + b input pin open. ? recommended circuit sample: *6 : if used exceeding t a = + 105 c, be sure to contact fujitsu for reliability limitations. warning: semiconductor devices can be permanently dama ged by application of stress (voltage, current, temperature, etc.) in excess of absolute ma ximum ratings. do not exceed these ratings. p-ch n-ch v cc r ? input/output equivalent circuits + b input (0 v to 16 v) limiting resistance protective diode
mb90350e series 53 2. recommended operating conditions (v ss = av ss = 0 v) * : if used exceeding t a = + 105 c, be sure to contact fujitsu for reliability limitations. warning: the recommended operating conditions are requir ed in order to ensure the normal operation of the semiconductor device. all of the device?s electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating cond ition ranges. operation outside these ranges may adversely affect re liability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit remarks min typ max power supply voltage v cc , av cc 4.0 5.0 5.5 v under normal operation 3.5 5.0 5.5 v under normal operation, when not using the a/d converter and not flash programming. 4.5 5.0 5.5 v when external bus is used. 3.0 ? 5.5 v maintains ram data in stop mode smoothing capacitor c s 0.1 ? 1.0 f use a ceramic capacitor or comparable capacitor of the ac c haracteristics. bypass capacitor at the v cc pin should be greater than this capacitor. operating temperature t a ? 40 ?+ 125 c* c c s ? c pin connection diagram
mb90350e series 54 3. dc characteristics (t a = ? 40 c to + 125 c, v cc = 5.0 v 10 % , f cp 24 mhz, v ss = av ss = 0 v) (continued) parameter sym- bol pin condition value unit remarks min typ max ?h? level input voltage (at v cc = 5 v 10 % ) v ihs ?? 0.8 v cc ? v cc + 0.3 v pin inputs if cmos hysteresis input levels are selected (except p12, p15, p44, p45, p50) v iha ?? 0.8 v cc ? v cc + 0.3 v pin inputs if automotive input levels are selected v iht ?? 2.0 ? v cc + 0.3 v pin inputs if ttl input levels are selected v ihs ?? 0.7 v cc ? v cc + 0.3 v p12, p15, p50 inputs if cmos input levels are selected v ihi ?? 0.7 v cc ? v cc + 0.3 v p44, p45 inputs if cmos hysteresis input levels are selected v ihr ?? 0.8 v cc ? v cc + 0.3 v rst input pin (cmos hysteresis) v ihm ?? v cc ? 0.3 ? v cc + 0.3 v md input pin ?l? level input voltage (at v cc = 5 v 10 % ) v ils ?? v ss ? 0.3 ? 0.2 v cc v pin inputs if cmos hysteresis input levels are selected (except p12, p15, p44, p45, p50) v ila ?? v ss ? 0.3 ? 0.5 v cc v pin inputs if automotive input levels are selected v ilt ?? v ss ? 0.3 ? 0.8 v pin inputs if ttl input levels are selected v ils ?? v ss ? 0.3 ? 0.3 v cc v p12, p15, p50 inputs if cmos input levels are selected v ili ?? v ss ? 0.3 ? 0.3 v cc v p44, p45 inputs if cmos hysteresis input levels are selected v ilr ?? v ss ? 0.3 ? 0.2 v cc v rst input pin (cmos hysteresis) v ilm ?? v ss ? 0.3 ? v ss + 0.3 v md input pin output ?h? voltage v oh normal outputs v cc = 4.5 v, i oh = ? 4.0 ma v cc ? 0.5 ?? v output ?h? voltage v ohi i 2 c current outputs v cc = 4.5 v, i oh = ? 3.0 ma v cc ? 0.5 ?? v
mb90350e series 55 (t a = ? 40 c to + 125 c, v cc = 5.0 v 10 % , f cp 24 mhz, v ss = av ss = 0 v) (continued) parameter sym- bol pin condition value unit remarks min typ max output ?l? voltage v ol normal outputs v cc = 4.5 v, i ol = 4.0 ma ?? 0.4 v output ?l? voltage v oli i 2 c current outputs v cc = 4.5 v, i ol = 3.0 ma ?? 0.4 v input leak current i il ? v cc = 5.5 v, v ss < v i < v cc ? 1 ? + 1a pull-up resistance r up p00 to p07, p10 to p17, p20 to p25, p30 to p37, rst ? 25 50 100 k ? pull-down resistance r down md2 ? 25 50 100 k ? except flash memory devices power supply current i cc v cc v cc = 5.0 v, internal frequency : 24 mhz, at normal operation. ? 48 60 ma v cc = 5.0 v, internal frequency : 24 mhz, at writing flash memory. ? 53 65 ma flash memory devices v cc = 5.0 v, internal frequency : 24 mhz, at erasing flash memory. ? 58 70 ma flash memory devices i ccs v cc = 5.0 v, internal frequency : 24 mhz, at sleep mode. ? 25 35 ma i cts v cc = 5.0 v, internal frequency : 2 mhz, at main timer mode ? 0.3 0.8 ma devices without ?t?-suffix ? 0.4 1.0 ma devices with ?t?-suffix i ctspll6 v cc = 5.0 v, internal frequency : 24 mhz, at pll timer mode, external frequency = 4 mhz ? 47ma
mb90350e series 56 (t a = ? 40 c to + 125 c, v cc = 5.0 v 10 % , f cp 24 mhz, v ss = av ss = 0 v) (continued) parameter sym- bol pin condition value unit remarks min typ max power supply current i ccl v cc v cc = 5.0 v, internal frequency: 8 khz, during stopping clock supervisor, at sub clock operation t a = + 25 c ? 70 140 a mb90f351e mb90f352e mb90351e mb90352e mb90f356e mb90f357e mb90356e mb90357e v cc = 5.0 v, internal frequency: 8 khz, during operating clock supervisor, at sub clock operation t a = + 25 c ? 100 200 a mb90f356e mb90f357e mb90356e mb90357e v cc = 5.0 v, internal cr oscillation/ 4 division, at sub clock operation t a = + 25 c ? 100 200 a mb90f356es mb90f357es mb90356es mb90357es v cc = 5.0 v, internal frequency: 8 khz, during stopping clock supervisor, at sub clock operation t a = + 25 c ? 120 240 a mb90f351te mb90f352te mb90351te mb90352te mb90f356te mb90f357te mb90356te mb90357te v cc = 5.0 v, internal frequency: 8 khz, during operating clock supervisor, at sub clock operation t a = + 25 c ? 150 300 a mb90f356te mb90f357te mb90356te mb90357te v cc = 5.0 v, internal cr oscillation/ 4 division, at sub clock operation t a = + 25 c ? 150 300 a mb90f356tes mb90f357tes mb90356tes mb90357tes
mb90350e series 57 (t a = ? 40 c to + 125 c, v cc = 5.0 v 10 % , f cp 24 mhz, v ss = av ss = 0 v) (continued) parameter sym- bol pin condition value unit remarks min typ max power supply current i ccls v cc v cc = 5.0 v, internal frequency: 8 khz, during stopping clock supervisor, at sub sleep t a = + 25 c ? 20 50 a mb90f351e mb90f352e mb90351e mb90352e mb90f356e mb90f357e mb90356e mb90357e v cc = 5.0 v, internal frequency: 8 khz, during operating clock supervisor, at sub sleep t a = + 25 c ? 60 200 a mb90f356e mb90f357e mb90356e mb90357e v cc = 5.0 v, internal cr oscillation/ 4 division, at sub sleep t a = + 25 c ? 60 200 a mb90f356es mb90f357es mb90356es mb90357es v cc = 5.0 v, internal frequency: 8 khz, at sub sleep t a = + 25 c ? 70 150 a mb90f351te mb90f352te mb90351te mb90352te mb90f356te mb90f357te mb90356te mb90357te v cc = 5.0 v, internal frequency: 8 khz, during operating clock supervisor, at sub sleep t a = + 25 c ? 110 300 a mb90f356te mb90f357te mb90356te mb90357te v cc = 5.0 v, internal cr oscillation/ 4 division, at sub sleep t a = + 25 c ? 110 300 a mb90f356tes mb90f357tes mb90356tes mb90357tes
mb90350e series 58 (continued) (t a = ? 40 c to + 125 c, v cc = 5.0 v 10 % , f cp 24 mhz, v ss = av ss = 0 v) parameter sym- bol pin condition value unit remarks min typ max power supply current i cct v cc v cc = 5.0 v, internal frequency: 8 khz, during stopping clock supervisor, at watch mode t a = + 25 c ? 10 35 a mb90f351e mb90f352e mb90351e mb90352e mb90f356e mb90f357e mb90356e mb90357e v cc = 5.0 v, internal frequency: 8 khz, during operating clock su- pervisor, at watch mode t a = + 25 c ? 25 150 a mb90f356e mb90f357e mb90356e mb90357e v cc = 5.0 v, internal cr oscillation/ 4 division, at watch mode t a = + 25 c ? 25 150 a mb90f356es mb90f357es mb90356es mb90357es v cc = 5.0 v, internal frequency: 8 khz, during stopping clock supervisor, at watch mode t a = + 25 c ? 60 140 a mb90f351te mb90f352te mb90351te mb90352te mb90f356te mb90f357te mb90356te mb90357te v cc = 5.0 v, internal frequency: 8 khz, during operating clock supervisor, at watch mode t a = + 25 c ? 80 250 a mb90f356te mb90f357te mb90356te mb90357te v cc = 5.0 v, internal cr oscillation/ 4 division, at watch mode t a = + 25 c ? 80 250 a mb90f356tes mb90f357tes mb90356tes mb90357tes i cch v cc = 5.0 v, at stop mode, t a = + 25 c ? 725 a devices without ?t?-suffix ? 60 130 a devices with ?t?-suffix input capacity c in other than c, av cc , av ss , avrh, v cc , v ss ?? 515pf
mb90350e series 59 4. ac characteristics (1) clock timing (t a = ? 40 c to + 125 c, v cc = 5.0 v 10 % , f cp 24 mhz, v ss = av ss = 0 v) (continued) parameter symbol pin value unit remarks min typ max clock frequency f c x0, x1 3 ? 16 mhz 1/2 (at pll stop) when using an oscillation circuit 4 ? 16 mhz 1 multiplied pll when using an oscillation circuit 4 ? 12 mhz 2 multiplied pll when using an oscillation circuit 4 ? 8mhz 3 multiplied pll when using an oscillation circuit 4 ? 6mhz 4 multiplied pll when using an oscillation circuit ?? 4mhz 6 multiplied pll when using an oscillation circuit x0 3 ? 24 mhz 1/2 (at pll stop), when using an external clock 4 ? 24 mhz 1 multiplied pll when using an external clock 4 ? 12 mhz 2 multiplied pll when using an external clock 4 ? 8mhz 3 multiplied pll when using an external clock 4 ? 6mhz 4 multiplied pll when using an external clock ?? 4mhz 6 multiplied pll when using an external clock f cl x0a, x1a ? 32.768 100 khz when using sub clock clock cycle time t cyl x0, x1 62.5 ? 333 ns when using an oscillation circuit x0 41.67 ? 333 ns when using an external clock t cyll x0a, x1a 10 30.5 ? s input clock pulse width p wh , p wl x0 10 ?? ns duty ratio should be about 30 % to 70 % . p whl , p wll x0a 5 15.2 ? s input clock rise and fall time t cr , t cf x0 ?? 5 ns when using an external clock
mb90350e series 60 (continued) (t a = ? 40 c to + 125 c, v cc = 5.0 v 10 % , f cp 24 mhz, v ss = av ss = 0 v) parameter symbol pin value unit remarks min typ max internal operating clock frequency (machine clock) f cp ? 1.5 ? 24 mhz when using main clock f cpl ?? 8.192 50 khz when using sub clock internal operating clock cycle time (machine clock) t cp ? 41.67 ? 666 ns when using main clock t cpl ? 20 122.1 ? s when using sub clock x0 t cyl t cf t cr 0.8 v cc 0.2 v cc p wh p wl x0a t cyll t cf t cr 0.8 v cc 0.2 v cc p whl p wll ? clock timing
mb90350e series 61 ? pll guaranteed operation range guaranteed operation range of mb90350e series * : when using crystal oscillator or ceramic osc illator, the maximum clock frequency is 16 mhz. external clock frequency and inte rnal operation clock frequency 5.5 3.5 4 1.5 24 4.0 guaranteed a/d converter operation range guaranteed pll operation range guaranteed operation range power supply voltage v cc (v) main clock f cp (mhz) 24 16 12 8 4.0 1.5 3 4 8 24 12 1/2 (pll off) 16 g ua r a nteed a/d converter oper a tion r a nge 1 2 3 4 6 internal clock f cp (mhz) external clock f c (mhz) *
mb90350e series 62 (2) reset standby input (t a = ? 40 c to + 125 c, v cc = 5.0 v 10 % , f cp 24 mhz, v ss = av ss = 0 v) * : oscillation time of oscillator is th e time that the amplitude reaches 90 % . in the crystal oscillator, the oscillation time is between several ms to tens of ms. in cerami c oscillators, the oscillation time is between hundreds of s to several ms. with an external cl ock, the oscillation time is 0 ms. parameter symbol pin value unit remarks min max reset input time t rstl rst 500 ? ns under normal operation oscillation time of oscillator* + 100 s ? s in stop mode, sub clock mode, sub sleep mode and watch mode 100 ? s in main timer mode and pll timer mode t rstl 0.2 v cc 0.2 v cc rst x0 90% of amplitude instruction execution oscillation stabilization waiting time oscillation time of oscillator internal operation clock internal reset 100 s 0.2 v cc rst t rstl 0.2 v cc under normal operation: in stop mode, sub clock mode, sub sleep mode and, watch mode:
mb90350e series 63 (3) power on reset (t a = ? 40 c to + 125 c, v cc = 5.0 v 10 % , f cp 24 mhz, v ss = av ss = 0 v) note : if you change the power supply voltage too rapidly, a power on reset may occur. we recommend that you start up smoothly by restraining voltages when changing the power supp ly voltage during operation, as shown in the figure below. perform while not using the pll clock. however, if voltage drops are within 1 v/s, you can operate while using the pll clock. (4) clock output timing (t a = ? 40 c to + 105 c, v cc = 5.0 v 10 % , v ss = 0.0 v, f cp 24 mhz) parameter symbol pin condition value unit remarks min max power on rise time t r v cc ? 0.05 30 ms power off time t off v cc 1 ? ms waiting time until power-on parameter symbol pin condition value unit remarks min max cycle time t cyc clk ? 62.5 ? ns f cp = 16 mhz 41.76 ? ns f cp = 24 mhz clk clk t chcl clk ? 20 ? ns f cp = 16 mhz 13 ? ns f cp = 24 mhz v cc t r t off 2.7 v 0.2 v 0.2 v 0.2 v v cc v ss 3 v hold s ram d a t a we recommend the s lope for a ri s e of 50 mv/m s m a xim u m. clk 2.4 v t cyc 2.4 v 0.8 v t chcl
mb90350e series 64 (5) bus timing (read) (t a = ?40 c to +105 c, v cc = 5.0 v 10 % , v ss = 0.0 v, f cp 24 mhz) * : number of ready cycles parameter sym- bol pin condition value unit min max ale pulse width t lhll ale ? t cp /2 ? 10 ? ns valid address ale time t avll ale, a21 to a16, ad15 to ad00 t cp /2 ? 20 ? ns ale address valid time t llax ale, ad15 to ad00 t cp /2 ? 15 ? ns valid address rd time t avrl a21 to a16, ad15 to ad00, rd t cp ? 15 ? ns valid address valid data input t avdv a21 to a16, ad15 to ad00 ? 5 t cp /2 ? 60 ns rd pulse width t rlrh rd (n*+3/2) t cp ? 20 ? ns rd valid data input t rldv rd , ad15 to ad00 ? (n*+3/2) t cp ? 50 ns rd data hold time t rhdx rd , ad15 to ad00 0 ? ns rd ale time t rhlh rd , ale t cp /2 ? 15 ? ns rd address valid time t rhax rd , a21 to a16 t cp /2 ? 10 ? ns valid address clk time t avch a21 to a16, ad15 to ad00, clk t cp /2 ? 16 ? ns rd clk time t rlch rd , clk t cp /2 ? 15 ? ns ale rd time t llrl ale, rd t cp /2 ? 15 ? ns
mb90350e series 65 a21 to a16 0.8 v 2.4 v 2.4 v 0.8 v t rhax ad15 to ad00 0.8 v 2.4 v 2.4 v 0.8 v address v il v ih v ih v il read data t rhdx t rldv t avdv clk t avch 2.4 v t rlch 2.4 v ale 2.4 v t lhll 2.4 v t rhlh 0.8 v t llax 2.4 v t avll rd t llrl t rlrh 0.8 v 2.4 v t avrl for 1 cycle of auto-ready
mb90350e series 66 (6) bus timing (write) (t a = ?40 c to +105 c, v cc = 5.0 v 10 % , v ss = 0.0 v, f cp 24 mhz) * : number of ready cycles parameter symbol pin condition value unit min max valid address wr time t avwl a21 to a16, ad15 to ad00, wr ? t cp ? 15 ? ns wr pulse width t wlwh wr (n*+3/2)t cp ? 20 ? ns valid data output wr time t dvwh ad15 to ad00, wr (n*+3/2)t cp ? 20 ? ns wr data hold time t whdx ad15 to ad00, wr 15 ? ns wr address valid time t whax a21 to a16, wr t cp /2 ? 10 ? ns wr ale time t whlh wr , ale t cp /2 ? 15 ? ns wr clk time t wlch wr , clk t cp /2 ? 15 ? ns clk t wlch 2.4 v ale t whlh 2.4 v wr (wrl , wrh ) t wlwh 0.8 v 2.4 v t avwl a21 to a16 0.8 v 2.4 v 2.4 v 0.8 v t whax ad15 to ad00 2.4 v 0.8 v address 0.8 v 2.4 v write data t dvwh 0.8 v 2.4 v t whdx for 1 cycle of auto-ready
mb90350e series 67 (7) ready input timing (t a = ?40 c to +105 c, v cc = 5.0 v 10 % , v ss = 0.0 v, f cp 24 mhz) note : if the rdy set-up time is insu fficient, use the auto-ready function. parameter sym- bol pin condition value units remarks min max rdy set-up time t ryhs rdy ? 45 ? ns f cp = 16 mhz 32 ? ns f cp = 24 mhz rdy hold time t ryhh rdy 0 ? ns clk 2.4 v ale rd /wr rdy (when wait is not used.) v ih v ih t ryhh rdy (when wait is used.) t ryhs v il
mb90350e series 68 (8) hold timing (t a = ?40 c to +105 c, v cc = 5.0 v 10 % , v ss = 0.0 v, f cp 24 mhz) note : there is more than 1 machine cycle from when hrq pin reads in until the hak is changed. parameter symbol pin condition value units min max pin floating hak time t xhal hak ? 30 t cp ns hak time pin valid time t hahv hak t cp 2 t cp ns hak each pin hi-z t hahv t xhal 2.4 v 0.8 v 2.4 v 2.4 v 0.8 v 0.8 v
mb90350e series 69 (9) uart 2/3 (t a = ? 40 c to + 125 c, v cc = 5.0 v 10 % , f cp 24 mhz, v ss = av ss = 0 v) * : refer to ? (1) clock timing? rating for t cp (internal operating clock cycle time). notes : ? ac characteristic in clk synchronous mode. ? c l is load capacity value of pins when testing. parameter symbol pin condition value unit min max serial clock cycle time t scyc sck2, sck3 internal shift clock mode output pins are c l = 80 pf + 1 ttl 8 t cp * ? ns sck sot delay time t slov sck2, sck3, sot2, sot3 ? 80 + 80 ns valid sin sck t ivsh sck2, sck3, sin2, sin3 100 ? ns sck valid sin hold time t shix sck2, sck3, sin2, sin3 60 ? ns serial clock ?h? pulse width t shsl sck2, sck3 external shift clock mode out- put pins are c l = 80 pf + 1 ttl 4 t cp ? ns serial clock ?l? pulse width t slsh sck2, sck3 4 t cp ? ns sck sot delay time t slov sck2, sck3, sot2, sot3 ? 150 ns valid sin sck t ivsh sck2, sck3, sin2, sin3 60 ? ns sck valid sin hold time t shix sck2, sck3, sin2, sin3 60 ? ns internal shift clock mode sck 2.4 v t scyc 0.8 v sot 0.8 v 2.4 v 0.8 v t slov sin v il v ih t ivsh v il v ih t shix
mb90350e series 70 (10) trigger input timing (t a = ? 40 c to + 125 c, v cc = 5.0 v 10 % , f cp 24 mhz, v ss = av ss = 0 v) parameter symbol pin condition value unit min max input pulse width t trgh t trgl int8 to int15, int9r to int11r, adtg ? 5 t cp ? ns external shift clock mode sck v ih t slsh v il sot 0.8 v 2.4 v t slov sin v il v ih t ivsh v il v ih t shix v ih v il t shsl v il v ih t trgh v il v ih t trgl int8 to int15, int9r to int11r, adtg
mb90350e series 71 (11) timer related resource input timing (t a = ? 40 c to + 125 c, v cc = 5.0 v 10 % , f cp 24 mhz, v ss = av ss = 0 v) (12) timer related resource output timing (t a = ? 40 c to + 125 c, v cc = 5.0 v 10 % , f cp 24 mhz, v ss = av ss = 0 v) parameter symbol pin condition value unit min max input pulse width t tiwh tin1, tin3,in0, in1, in4 to in7 ? 4 t cp ? ns t tiwl parameter symbol pin condition value unit min max clk t out change time t to tot1, tot3, ppg4, ppg6, ppg8 to ppgf ? 30 ? ns v il v ih t tiwh v il v ih t tiwl tin1, tin3, in0, in1, in4 to in7 clk 2.4 v 0.8 v 2.4 v t to tot1, tot3, ppg4, ppg6 ppg8 to ppgf
mb90350e series 72 (13) i 2 c timing (t a = ? 40 c to + 125 c, v cc = av cc = 5.0 v 10 % , f cp 24 mhz, v ss = av ss = 0 v) *1 : r,c : pull-up resistor and load capacitor of the scl and sda lines. *2 : the maximum t hddat has to meet at least that the device does not exceed the ?l? width (t low ) of the scl signal. *3 : a fast-mode i 2 c -bus device can be used in a standard-mode i 2 c-bus system, but the requirement t sudat 250 ns must be met. *4 : for use at over 100 khz, set the machine clock to at least 6 mhz. *5 : refer to ? ? note of sda, scl set-up time?. parameter symbol condition standard-mode fast-mode* 4 unit min max min max scl clock frequency f scl r = 1.7 k ? , c = 50 pf* 1 0 100 0 400 khz hold time for (re peated) start condition sda scl t hdsta 4.0 ? 0.6 ? s ?l? width of the scl clock t low 4.7 ? 1.3 ? s ?h? width of the scl clock t high 4.0 ? 0.6 ? s set-up time for a repeated start condition scl sda t susta 4.7 ? 0.6 ? s data hold time scl sda t hddat 0 3.45* 2 00.9* 3 s data set-up time sda scl t sudat 250* 5 ? 100* 5 ? ns set-up time for stop condition scl sda t susto 4.0 ? 0.6 ? s bus free time between stop condition and start condition t bus 4.7 ? 1.3 ? s sda scl 6 t cp note of sda, scl set-up time input data set-up time
mb90350e series 73 note : the rating of the in put data set-up time in the device connecte d to the bus cannot be satisfied depending on the load capacitance or pull-up resistor. be sure to adjust the pull-up resistor of sda and scl if the rating of the input dat a set-up time cannot be satisfied. sda scl t bus t low f scl t hddat t high t sudat t hdsta t susta t hdsta t susto timing definition
mb90350e series 74 5. a/d converter ( t a = ? 40 c to + 125 c, 3.0 v avrh, v cc = av cc = 5.0 v 10 % , f cp 24 mhz, v ss = av ss = 0 v ) * : if a/d converter is not operating, a current when cpu is stopped is applicable (v cc = av cc = avrh = 5.0 v) . parameter symbol pin value unit remarks min typ max resolution ?? ? ? 10 bit total error ?? ? ? 3.0 lsb nonlinearity error ?? ? ? 2.5 lsb differential nonlinearity error ?? ? ? 1.9 lsb zero reading voltage v ot an0 to an14 av ss ? 1.5 av ss + 0.5 av ss + 2.5 v full scale reading voltage v fst an0 to an14 avrh ? 3.5 avrh ? 1.5 avrh + 0.5 v compare time ?? 1.0 ? 16500 s 4.5 v av cc 5.5 v 2.0 4.0 v av cc < 4.5 v sampling time ?? 0.5 ? s 4.5 v av cc 5.5 v 1.2 4.0 v av cc < 4.5 v analog port input current i ain an0 to an14 ? 0.3 ? + 0.3 a analog input voltage range v ain an0 to an14 av ss ? avrh v reference voltage range ? avrh av ss + 2.7 ? av cc v power supply current i a av cc ? 3.5 7.5 ma i ah av cc ?? 5 a* reference voltage supply current i r avrh ? 600 900 a i rh avrh ?? 5 a* offset between channels ? an0 to an14 ?? 4lsb
mb90350e series 75 notes on a/d converter section ? about the external impedance of th e analog input and its sampling time a/d converter with sample and hold circuit. if the exte rnal impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting a/d conversion precision. therefore to satisfy the a/d conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the register value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. also if the sampling time cannot be suffic ient, connect a capacitor of about 0.1 f to the analog input pin. an a log inp u t e qu iv a lence circ u it on a t sa mpling note : the v a l u e i s reference v a l u e. r c an a log inp u t comp a r a tor mb90f 3 51e( s ), mb90f 3 52e( s ), mb90f 3 56e( s ), mb90f 3 57e( s ), mb90f 3 51te( s ), mb90f 3 52te( s ),mb90f 3 56te( s ), mb90f 3 57te( s ) c r 4.5 v av cc 5.5 v 2.0 k ? (m a x) 16.0 pf (m a x) 4.0 v av cc 4.5 v 8 .2 k ? (m a x) 16.0 pf (m a x) mb90v 3 40e-101/102/10 3 /104, mb90 3 51e( s ), mb90 3 52e( s ),mb90 3 56e( s ), mb90 3 57e( s ), mb90 3 51te( s ), mb90 3 52te( s ),mb90 3 56te( s ), mb90 3 57te( s ) c r 4.5 v av cc 5.5 v 2.0 k ? (m a x) 14.4 pf (m a x) 4.0 v av cc 4.5 v 8 .2 k ? (m a x) 14.4 pf (m a x)
mb90350e series 76 ? flash memory device ? mask rom device ? about the error values of relative errors grow larger, as |avrh ? av ss | becomes smaller. rel a tion b etween extern a l imped a nce a nd minim u m sa mpling time 4.5 v av cc 5.5 v [extern a l imped a nce = 0 k ? to 100 k ? ] minim u m sa mpling time [ s ] extern a l imped a nce [k ? ] 0 5 10 15 20 25 3 0 3 5 10 20 3 0 40 50 60 70 8 0 90 100 4.0 v av cc 4.5 v 4.5 v av cc 5.5 v [extern a l imped a nce = 0 k ? to 20 k ? ] minim u m sa mpling time [ s ] extern a l imped a nce [k ? ] 0 1 2 3 4567 8 2 4 6 8 10 12 14 16 1 8 20 4.0 v av cc 4.5 v (mb90f 3 51e( s ), mb90f 3 52e( s ), mb90f 3 56e( s ), mb90f 3 57e( s ), mb90f 3 51te( s ), mb90f 3 52te( s ),mb90f 3 56te( s ), mb90f 3 57te( s )) 00 rel a tion b etween extern a l imped a nce a nd minim u m sa mpling time 4.5 v av cc 5.5 v [extern a l imped a nce = 0 k ? to 100 k ? ] minim u m sa mpling time [ s ] extern a l imped a nce [k ? ] 0 5 10 15 20 25 3 0 3 5 10 20 3 0 40 50 60 70 8 0 90 100 4.0 v av cc 4.5 v 4.5 v av cc 5.5 v [extern a l imped a nce = 0 k ? to 20k ? ] minim u m sa mpling time [ s ] extern a l imped a nce [k ? ] 0 1 2 3 4567 8 2 4 6 8 10 12 14 16 1 8 20 4.0 v av cc 4.5 v (mb90v 3 40e-101/102/10 3 /104, mb90 3 51e( s ), mb90 3 52e( s ), mb90 3 56e( s ), mb90 3 57e( s ), mb90 3 51te( s ), mb90 3 52te( s ), mb90 3 56te( s ), mb90 3 57te( s )) 00
mb90350e series 77 6. definition of a/d converter terms (continued) resolution : analog variation that is recognized by an a/d converter. non linearity error : deviation between a line across ze ro-transition line ( ?00 0000 0000? ?00 0000 0001? ) and full-scale transition line ( ?11 1111 1110? ?11 1111 1111? ) and actual conversion characteristics. differential linearity error : deviation of input voltage, which is required fo r changing output code by 1 lsb, from an ideal value. total error : difference between an actual value a nd a theoretical value. a total error includes zero transition error, full-scale transition error, and linear error. 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h av ss avrh v nt 1.5 lsb 0.5 lsb {1 lsb (n ? 1) + 0.5 lsb} actual conversion characteristics (actual measurement value) actual conversion characteristics ideal characteristics digital output analog input total error total error of digital output ?n? = v nt ? {1 lsb (n ? 1) + 0.5 lsb} 1 lsb [lsb] 1 lsb (ideal value) = avrh ? av ss 1024 [v] n : a/d converter digital output value v ot (ideal value) = av ss + 0.5 lsb [v] v fst (ideal value) = avrh ? 1.5 lsb [v] v nt : a voltage at which digita l output transits from (n ? 1) to n.
mb90350e series 78 (continued) 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h av ss avrh av ss avrh n + 1 h n h n ? 1 h n ? 2 h v ot ( actual measurement value ) {1 lsb (n ? 1) + v ot } actual conversion characteristics v fst (actual measurement value) v nt (actual measurement value) actual conversion characteristics ideal characteristics actual conversion characteristics actual conversion characteristics ideal characteristics digital output digital output analog input analog input v nt (actual measurement value) v (n + 1) t (actual measurement value) non linearity error differential linearity error non linearity error of digital output n = v nt ? {1 lsb (n ? 1) + v ot } 1 lsb [lsb] differential linearity error of digital output n = v ( n+1 ) t ? v nt 1 lsb ? 1 lsb [lsb] v fst ? v ot 1022 [v] 1 lsb = n : a/d converter digital output value v ot : voltage at which digital output transits from ?000 h ? to ?001 h ?. v fst : voltage at which digital output transits from ?3fe h ? to ?3ff h ?.
mb90350e series 79 7. flash memory program/erase characteristics ? dual operation flash memory * : corresponding value comes from the technology reliability evaluation result. (using arrhenius equation to translate high temperatur e measurements test result into normalized value at + 85 c) parameter conditions value unit remarks min typ max sector erase time (4 kbytes sector) t a = + 25 c v cc = 5.0 v ? 0.2 0.5 s excludes programming prior to erasure sector erase time (16 kbytes sector) ? 0.5 7.5 s excludes programming prior to erasure chip erase time ? 4.6 ? s excludes programming prior to erasure word (16-bit width) programming time ? 64 3600 s except for the overhead time of the system level program/erase cycle ? 10000 ?? cycle flash memory data retention time average t a = + 85 c 20 ?? year *
mb90350e series 80 ordering information (continued) part number package remarks mb90f351epmc 64-pin plastic lqfp fpt-64p-m23 12.0 mm , 0.65 mm pitch dual operation flash memory products (64 kbytes) mb90f351espmc mb90f351tepmc mb90f351tespmc mb90f356epmc mb90f356espmc mb90f356tepmc mb90f356tespmc mb90f352epmc 64-pin plastic lqfp fpt-64p-m23 12.0 mm , 0.65 mm pitch dual operation flash memory products (128 kbytes) mb90f352espmc mb90f352tepmc mb90f352tespmc mb90f357epmc mb90f357espmc mb90f357tepmc mb90f357tespmc mb90351epmc 64-pin plastic lqfp fpt-64p-m23 12.0 mm , 0.65 mm pitch mask rom products (64 kbytes) mb90351espmc mb90351tepmc MB90351TESPMC mb90356epmc mb90356espmc mb90356tepmc mb90356tespmc mb90352epmc 64-pin plastic lqfp fpt-64p-m23 12.0 mm , 0.65 mm pitch mask rom products (128 kbytes) mb90352espmc mb90352tepmc mb90352tespmc mb90357epmc mb90357espmc mb90357tepmc mb90357tespmc
mb90350e series 81 (continued) part number package remarks mb90f351epmc1 64-pin plastic lqfp fpt-64p-m24 10.0 mm , 0.50 mm pitch dual operation flash memory products (64 kbytes) mb90f351espmc1 mb90f351tepmc1 mb90f351tespmc1 mb90f356epmc1 mb90f356espmc1 mb90f356tepmc1 mb90f356tespmc1 mb90f352epmc1 64-pin plastic lqfp fpt-64p-m24 10.0 mm , 0.50 mm pitch dual operation flash memory products (128 kbytes) mb90f352espmc1 mb90f352tepmc1 mb90f352tespmc1 mb90f357epmc1 mb90f357espmc1 mb90f357tepmc1 mb90f357tespmc1 mb90351epmc1 64-pin plastic lqfp fpt-64p-m24 10.0 mm , 0.50 mm pitch mask rom products (64 kbytes) mb90351espmc1 mb90351tepmc1 MB90351TESPMC1 mb90356epmc1 mb90356espmc1 mb90356tepmc1 mb90356tespmc1 mb90352epmc1 64-pin plastic lqfp fpt-64p-m24 10.0 mm , 0.50 mm pitch mask rom products (128 kbytes) mb90352espmc1 mb90352tepmc1 mb90352tespmc1 mb90357epmc1 mb90357espmc1 mb90357tepmc1 mb90357tespmc1 mb90v340e-101 299-pin ceramic pga pga-299c-a01 device for evaluation mb90v340e-102 mb90v340e-103 mb90v340e-104
mb90350e series 82 package dimensions please confirm the latest package dimension by following url. http://edevice.fujitsu.com/f j/datasheet/ef-ovpklv.html (continued) 64-pin pl as tic lqfp le a d pitch 0.65 mm p a ck a ge width p a ck a ge length 12.0 12.0 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 1.70 mm max code (reference) p-lfqfp64-12 12-0.65 64-pin pl as tic lqfp (fpt-64p-m2 3 ) (fpt-64p-m2 3 ) c 200 3 fujit s u limited f640 3 4 s -c-1-1 0.65(.026) 0.10(.004) 1 16 17 3 2 49 64 33 4 8 * 12.00 0.10(.472 .004) s q 14.00 0.20(.551 .00 8 ) s q index 0. 3 2 0.05 (.01 3 .002) m 0.1 3 (.005) 0.145 0.055 (.0057 .0022) "a" .059 ? .004 +.00 8 ? 0.10 +0.20 1.50 0~ 8 ? 0.25(.010) (mo u nting height) 0.50 0.20 (.020 .00 8 ) 0.60 0.15 (.024 .006) 0.10 0.10 (.004 .004) det a il s of "a" p a rt ( s t a nd off) dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s note 1) * : the s e dimen s ion s do not incl u de re s in protr us ion. note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 )pin s width do not incl u de tie ba r c u tting rem a inder.
mb90350e series 83 (continued) please confirm the latest package dimension by following url. http://edevice.fujitsu.com/f j/datasheet/ef-ovpklv.html 64-pin pl as tic lqfp le a d pitch 0.50 mm p a ck a ge width p a ck a ge length 10.0 10.0 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 1.70 mm max weight 0. 3 2g code (reference) p-lfqfp64-10 10-0.50 64-pin pl as tic lqfp (fpt-64p-m24) (fpt-64p-m24) lead no. det a il s of "a" p a rt 0.25(.010) ( s t a nd off) (.004.004) 0.100.10 (.024.006) 0.600.15 (.020.00 8 ) 0.500.20 1.50 +0.20 ?0.10 +.00 8 ?.004 .059 0 ? ~ 8 ? "a" 0.0 8 (.00 3 ) (.006.002) 0.1450.055 0.0 8 (.00 3 ) m (.00 8 .002) 0.200.05 0.50(.020) 12.000.20(.472.00 8 ) s q 10.000.10(. 3 94.004) s q index 49 64 33 4 8 17 3 2 16 1 2005 fujit s u limited f640 3 6 s -c-1-1 c (mo u nting height) * dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s note 1) * : the s e dimen s ion s do not incl u de re s in protr us ion. note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 )pin s width do not incl u de tie ba r c u tting rem a inder.
mb90350e series 84 main changes in this edition the vertical lines marked in the left side of the p age show the changes. page section change results ?? added the following part numbers. mb90356e(s)/te(s),mb90f356e(s)/te(s), mb90357e(s)/te(s), mb90f357e(s)/te(s), mb90v340e-103/104) 1 description added a description of the "clock supervisor". 2 features added a description of the "clock supervisor". 13 packages and product correspondence changed the description of "fpt-64p-m24" as follows: * removed the table footnote "* : this device is under development." 27 handling devices added section "19.internal cr oscillation circuit". 40 i/o map added the ?clock supervisor control register?. 56 electrical characteristics 3. dc characteristics added the ratings for the "c lock supervisor" to the "i ccl " section of the power supply current ratings. 57 added the ratings for the "c lock supervisor" to the "i ccls " section of the power supply current ratings. 58 added the ratings for the "c lock supervisor" to the "i cct " section of the power supply current ratings. 81 ordering information removed the footnot e asterisks from the "dual operation flash memory products*" and "mask rom products*" of the "fpt-64p-m24" package. removed the table footnote "* : this device is under development."
mb90350e series f0701 the information for microcontroller suppor ts is shown in the following homepage. http://www.fujitsu.com/global/s ervices/microelectronics/produ ct/micom/support/index.html fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any ot her right of fujitsu or any third party or does fujitsu warrant non-in fringement of any third-party?s intellectual property right or othe r right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremel y high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, ai rcraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon syst em), or (2) for use requiring extremely high reliability (i.e., su bmersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design m easures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. the company names and brand names herein are the trademarks or registered trademarks of their respective owners. edited business promotion dept.

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